STW4510 datasheet(14/57 Pages) STMICROELECTRONICS

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Functional description

STw4510

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3.2

Digital control module

This module describes the interfaces used to program the device and the related registers.

3.2.1

State machine

Each state is described here below and represented in

Figure 2

OFF: In this mode the STw4510 is switched off. Off is when Pon signal = “0”, when battery

level is below 2.4V or when thermal shutdown is activated (in this particular case: not a

permanent state). There is no power supply. The only active cell is the Vbat level detection.

OSC_START: Oscillator is enabled and the power up module is waiting for the rising edge of

the internal signal ‘Osc_OK’ to start power up sequence. This state duration is 300 µs.

START_BIAS: Bias, reference and thermal shut-down are enabled, a counter is activated to

wait for rising edge of internal signals ‘pdn_regulators’. This state duration has a typical

value of 7.8 ms and a worst case value of 9.46 ms.

START_PM: soft start period, during this state, Vdig, Vsdc2 progressively reach their final

values. At the end of this state, processor power supplies (Vdig, Vsdc2) are available,

internal signal ‘pdn_ls’ is set to 1 and then the device can allow I2C communication, output

power supply monitoring and application. Typical duration of this state is 0.67ms and never

goes over than the maximum duration of 1 ms.

OFF2: STw4510 is waiting for the 32 kHz processor signal. This state has an indeterminate

duration. (if 32 kHz is present during the states describes above, it has no effect on

STw4510 behavior, 32 kHz signal is taking in account by STw4510 at the end of START_PM

state, the duration of this state is 0.4 ms minimum).

RESET: STw4510 forces a reset during 36*1/32 kHz period (duration of 1.13ms) before

setting Res_pro signal high. This signal Res_pro is high if Pon is high and 32kHz clock

available.

SLEEP & Vsdc1_OFF: Sleep mode (

Section 3.2.3) and Vsdc1_OFF mode (Section 3.2.4)

are required by processor by setting Pwren signal at low level. Then VddOK signal is forced

to “0”, Step Down DC/DC converter Vsdc2, and LDO Vana_i (i = 1 to 3) switch to sleep

mode, SMPS converter Vsdc1 switches off and wait for Pwren signal at high level

(

Figure 3).

WAKE-UP: From sleep mode and Vsdc1_OFF, the processor requests to switch back to

high power mode (HPM) and ON mode for Vsdc1 by setting Pwren to high level. Thus the

device switches regulators from Low power mode (sleep) to high power mode and informs

processor with VddOK signal at high level (

Figure 3).

Note:

Sleep mode has no effect on Vdig nor Vmmc.

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