STW4510 datasheet(16/57 Pages) STMICROELECTRONICS

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Functional description

STw4510

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Figure 3.

Switching from high power mode to sleep/Vsdc1_OFF mode

3.2.2

POWER OFF / VddOK

●

In case of VddOK falling edge (under voltage on Vsdc1, Vsdc2 detected), the

processor is reset (Res_pro low during 1.8 ms minimum) and started again with no

time-out. (See

Figure 4)

●

In case of VddOK falling down edge (under Pwren falling edge) the processor is not

reset (Res_pro keeps its high level)

●

In case of Pon falling edge (switch off of STw4510 from the main processor), the

processor is also reset with no time-out. It is considered that clean switch off between

modem and processor is done by software directly.

Internal_osc

Pdn_regulator

(int. signal)

VddOK

Clock32K_in

PWREN

Vdig @ 1.2V

Vsdc1 @ 1.2V

Vsdc2 @ 1.8V

Vana[i] & Vmmc

controlled by I2C

Voutputs

STw4510

Vdig @ 1.2V still active

Vsdc1 in OFF state

Vsdc2 @ 1.8V in SLEEP mode (low

current capability)

Vana[i] in SLEEP mode (low current capability)

Vmmc not affected by sleep mode

Vsdc1 @ 1.2V,

available after

stabilization time

Vdig @ 1.2V still active

Vsdc2 @ 1.8V

1ms max

SLEEP / OFF controlled by PWREN

HPM

PM00128

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