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STW4510 データシート(PDF) 45 Page - STMicroelectronics |
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STW4510 データシート(HTML) 45 Page - STMicroelectronics |
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45 / 57 page ![]() Obsolete Product(s) - Obsolete Product(s) STw4510 Electrical and timing characteristics 45/57 Vmmc Table 23. LDO regulator - Vmmc Symbol Description Test conditions Min. Typ. Max. Units VMMC regulator specifications (PDN_VMMC = 1) VBAT Input voltage VOUT = 3 V VOUT = 2.85 V VOUT = 2.5 V VOUT = 1.8 V 3.25 3.1 2.75 2.7 3.6 5.5 V VOUT Output voltage -3% 3 2.85 2.5 1.8 +3% V IOUT (1) Output current 150 mA ISHORT (1) Short circuit current limitation 240 360 600 mA IQ (2) Quiescent current IOUT = 0 mA 26 µA ILKG Power-down current 1 µA PSRR Power supply rejection IOUT = 150 mA Vpp = 0.3 V f < 20 kHz 40 dB LIR Line regulation VBAT: [3.1; 5.5]V 10 mV LDR Load regulation IOUT= [1; 150] mA 10 mV LIRT Transient line regulation VOUT=2.85 V VBAT: 3.1 to 3.4V tR = tF = 10 µs. 2mV LDRT Transient load regulation IOUT = [1; 150] mA tR = tF = 1 µs 25 mV tS Settling time OFF->ON IOUT = 0 mA 100 µs tD Discharge time ON>OFF IOUT = 0 mA 1 ms 1. Guaranteed by design 2. Quiescent current defined is the current measured on the power supply voltage dedicated to the Vmmc |
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