STW4510 datasheet(33/57 Pages) STMICROELECTRONICS

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STw4510

Functional description

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3.3.7

Vdig

This LDO is dedicated, for example, to supply a alive digital part of peripherals associated to

a processor.

Main features

●

Programmable output voltage: Vdig_sel[1:0] pads - 1 V, 1.2 V, 1.5 V (to be fixed in the

application by internal routing to Vbat or ground)

●

Two power domains:

–

High power mode, 100mA full load when 1V output voltage selected, otherwise

250 mA full load.

–

Power down mode when regulator is switched off and there is no power

consumption. Switch on and off is controlled by Pon signal. Pon is set to “0” and

Vdig is switched off. Vdig has its voltage output available once Pon is set to “1”

and the start-up sequence has ended.

●

Default setting defined by start-up device configuration.

●

Positive supply could be generated by Vsdc2 step down DC/DC converter.

3.3.8

Vmmc power supply

This block provides the power supply (1.8 V, 2.5 V, 2.85 V or 3 V) requested for MultiMedia

Cards applications. This LDO can also be used for any other feature in the application.

Main features

●

Programmable output voltage by I2C (1.8 V, 2.5 V, 2.85 V or 3 V)

●

2 power domains:

–

High power mode, 150 mA full load

–

Power down mode when regulator is switched off via I2C and there is no power

consumption. Leakage is reduce to 1 µA.

●

Specification guaranteed with battery voltages from 2.7 V up to 5.5 V (minimum Vbat

values are indicated in

Table 23).

3.3.9

Power supply monitoring

This block monitors the Vsdc1 and Vsdc2 output voltage. If Vsdc1 or Vsdc2 drop below the

threshold the processor is reset.

This feature can be desactivated by setting en_monitoring bit of Power control register

(

Power control register @ 08h) to “0”.

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