STW4510 datasheet(31/57 Pages) STMICROELECTRONICS

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Functional description

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3.3.3

Vsdc2 step down DC/DC converter

The Vsdc2 step down DC/DC converter is designed to supply the IOs of the processor and

its peripherals (memories DDR-SDRAM for example).

Vsdc2 output has a fixed 1.8V output voltage.

The step down DC/DC converter runs on the internal RC oscillator.

Main features

●

Fixed 1.8 V output voltage

●

Three power domains:

–

High power mode - 600 mA full load

–

Sleep mode with a 10 mA low current capability. (

Table 19: Vsdc2 DC/DC step-

down converter)

Fast switching from sleep mode (low current output capability) to high power

mode. The step down DC/DC converter is in sleep mode when the portable

processor controls the Pwren signal to 0 indicating that the portable processor is

able to switch to sleep mode. VddOK signal indicates to the processor that Vsdc2

supply is in the specified range.

–

Power down mode when step down DC/DC converter is switched off, no

consumption. The ON/OFF sequence is controlled by Pon; Pon signal is set to 0

and Vsdc1 is switched off.

●

Soft start circuitry from power off to high power mode

●

Specification guaranteed with input voltage from 2.7 V up to 5.5 V

Note:

The definition of sleep mode is given in Section 3.2.3.

3.3.4

Vana1

This LDO is dedicated, for example, to supply an analog part of a peripheral associated to a

processor.

Main features

●

Programmable output voltage: Vana1_sel[1:0] pads - 1.5, 1.8, 2.5, 2.8 V (to be fixed in

the application by routing to Vbat or ground). On the 4 mm x 4 mm package the

selection of output voltage values is limited to Sel[0] and the available voltage values

are 2.5 V and 2.8 V.

●

Three power domains:

–

High power mode, 150 mA full load

–

Sleep mode with a low current capability of 0.5 mA full load (

Table 20)

–

Power down mode when regulator is switched off and there is no power

consumption (pdn-vana1 bit of application control register (

Application control

06h), it is recommended to use only the pdn_vana1 control bit.

●

Default setting defined by start-up device configuration

●

Specification guaranteed with battery voltages from 2.7 V up to 5.5 V (battery voltage

of 3.5 V for a LDO output of 3.3V with full characteristics available).

Note:

The definition of sleep mode is given in Section 3.2.3.

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