STW4510 datasheet(15/57 Pages) STMICROELECTRONICS

15 / 57 page

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Product(s)

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Product(s)

STw4510

Functional description

15/57

Figure 2.

State machine: Start-up timing

Vsdc2, Vdig are started with internal pdn_regulators signals.

I2C is available after internal ‘pdn_ls’ signal is set to “1”.

Processor reset done on the Res_pro signal is synchronous of the 32 kHz clock.

During power-up, Pwren is masked. Nevertheless, Vsdc1 power supply that is controlled by

Pwren, is in OFF state during the starting phase and this up to internal signal “pdn_ls =1”

and then, the control of the Vsdc1 is done via the external Pwren signal.

The soft start feature limits the peak current sink in the Vbat supply when a supply is set to

ON state.

Pon

VBat

Internal_osc

OTP

initialization

Osc-start

300us

Start_biais

(9.5ms max.)

Battery voltage avalaible

Pdn_regulator

(int. signal)

Start_PM

(1ms max.)

VddOK

Clock32K_in

OFF2

(0.4ms)

RESET 1.13ms

Processor reset done => active state

Res_pro

PWREN = 1 => Full power supply available

PWREN = 0 => OFF or SLEEP Mode available

I2C of PMIC available

PWREN

12.33ms max.

Vdig @ 1.2V

Vsdc1 @ 1.2V

controlled by pwren

Vsdc2 @ 1.8V

Vana[i] & Vmmc controlled by I2C

Voutputs

STw4510

1ms max.

PWREN internally masked

1ms max.

Internal signal

pdn_ls

PM00126

Pon is needed to start every SMPS and LDO ON

Processor in reset mode

PWREN controlled by processor

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