STW4510 datasheet(44/57 Pages) STMICROELECTRONICS

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Electrical and timing characteristics

STw4510

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Vdig

Table 22.

LDO regulator - Vdig

Symbol

Description

Test conditions

Min.

Typ.

Max.

Units

Vdig regulator in high power mode (pdn_vdig = 1); Otherwise specified Vin = Vsdc2 (1.8 V)

VIN

Vsdc2 input power

supply

Vdig = 1 V/1.2 V

-3%

1.8

+3%

VBAT input power supply Vdig = 1.5 V

2.7

3.6

5.5

VOUT

Output voltage

Vdig_sel[1:0] pads

-3 %

1.0

1.2

1.5

+3 %

IOUT

(1)

Output current

Vdig: 1 V

100

Vdig: 1.2 V/1.5 V

250

ISHORT

(1)

Short-circuit limitation

330

800

(2)

Quiescent current

IOUT = 0 mA

µA

ILKG

Power-down current

1.5

µA

Rising time

(10 % to 90 %)

Vdig = 1.2 V

IOUT = 10 mA

0.7

Lir

Line regulation

VBAT: [2.7; 5.5] V

Ldr

Load regulation

IOUT: [0.1; 250] mA

Lirt

Transient line regulation

Vdig = 1.2 V

IOUT = 150 mA

Δ VBAT= 300 mV

tR = tF = 10 µs

1mV

Ldrt

Transient load regulation

Vdig = 1.2 V

IOUT= [1; 250] mA

tR = tF = 1 µs

Guaranteed by design

Quiescent current defined is the current measured on the power supply voltage dedicated to the Vdig

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