STW4510 datasheet(17/57 Pages) STMICROELECTRONICS

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Functional description

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Figure 4.

VddOK block diagram

3.2.3

Sleep mode

STw4510 sleep mode is only active with the presence of the 32kHz clock on pin Clk32_in

and STw4510 power supplies Vsdc2, Vana1, Vana2, Vana3 go into sleep. The voltage is still

present on the power supply output with current capability reduced. Sleep mode is activated

each time the Pwren signal is at low level (logical 0).

To exit sleep mode state it is mandatory to have the Pwren signal at high level (logical 1).

In this present version, sleep mode is available each time Pwren = 0.

When Pwren = 0, some application may require that Vsdc2 and/or Vana(I) remain in high

power mode. STw4510 may be able to comply with this requirement. For more information

please contact the STMicroelectronics sales office.

3.2.4

Vsdc1_OFF mode

Vsdc1_OFF mode is only referenced to the Pwren signal. When Pwren signal is high

(logical level 1) the Vsdc1 DC/DC regulator is in high power mode and the application

processor can be supplied. In the case of Pwren is low level (logical 0) Vsdc1 is switched off

and the consumption is reduced to the leakage current.

3.2.5

Power supplies at start-up

After Pon, and considering the state machine, different regulators (Vana(i), Vdig) can be

switched ON or OFF at start-up with the default output voltage configured by the selection

pin available.

STW4510 データシート(PDF) 17 Page - STMicroelectronics