GD25LB64C datasheet(24/70 Pages) GIGADEVICE

24 / 70 page

1.8V Uniform Sector

Dual and Quad Serial Flash

GD25LB64C

7.9 Quad Output Fast Read (6BH)

The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being

latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1

and IO0. The command sequence is shown in followed Figure10. The first byte addressed can be at any location. The

address is automatically incremented to the next higher address after each byte of data is shifted out.

Figure10. Quad Output Fast Read Sequence Diagram

7.10 Dual I/O Fast Read (BBH)

The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input

the 3-byte address (A23-0) and a

“Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit being latched in

during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The

command sequence is shown in followed Figure11. The first byte addressed can be at any location. The address is

automatically incremented to the next higher address after each byte of data is shifted out.

Dual I/O Fast Read with

“Continuous Read Mode”

The Dual I/O Fast Read command can further reduce command overhead through setting the

“Continuous Read

Mode

” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next

Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The

command sequence is shown in followed Figure11. If the

“Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next

command requires the first BBH command code, thus returning to normal operation. A

“Continuous Read Mode” Reset

command can be used to reset (M5-4) before issuing normal command.

Command

6BH

CS#

SCLK

IO0

IO1

High-Z

9 10

28 29 30 31

23 22 21

24-bit address

34 35 36 37

38 39

Byte1

42 43 44 45

46 47

Dummy Clocks

IO2

High-Z

IO3

High-Z

CS#

SCLK

IO0

IO1

Byte2 Byte3 Byte4

IO2

IO3

GD25LB64C データシート(PDF) 24 Page - GigaDevice Semiconductor (Beijing) Inc.

GD25LB64C データシート(HTML) 24 Page - GigaDevice Semiconductor (Beijing) Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

データシートダウンロード

リンク URL

GD25LB64C データシート(PDF) 24 Page - GigaDevice Semiconductor (Beijing) Inc.

GD25LB64C データシート(HTML) 24 Page - GigaDevice Semiconductor (Beijing) Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

データシート ダウンロード

リンク URL

データシートダウンロード