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SPC58EN80C3RMSBY データシート(PDF) 53 Page - STMicroelectronics |
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SPC58EN80C3RMSBY データシート(HTML) 53 Page - STMicroelectronics |
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53 / 158 page  DS11734 Rev 6 53/158 SPC584Nx, SPC58ENx, SPC58NNx Electrical characteristics 71 ΔTUE12 CC D TUE degradation due to VDD_HV_ADR offset with respect to VDD_HV_ADV VIN < VDD_HV_ADV VDD_HV_ADR − VDD_HV_ADV ∈ [0:25 mV] –1 1 LSB (12b) VIN < VDD_HV_ADV VDD_HV_ADR − VDD_HV_ADV ∈ [25:50 mV] –2 2 VIN < VDD_HV_ADV VDD_HV_ADR − VDD_HV_ADV ∈ [50:75 mV] –4 4 VIN < VDD_HV_ADV VDD_HV_ADR − VDD_HV_ADV ∈ [75:100 mV] –6 6 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR − VDD_HV_ADV ∈ [0:25 mV] –2.5 2.5 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR − VDD_HV_ADV ∈ [25:50 mV] –4 4 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR − VDD_HV_ADV ∈ [50:75 mV] –7 7 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR − VDD_HV_ADV ∈ [75:100 mV] –12 12 TUEINJ2 CC T TUE degradation addition, due to current injection in IINJ2 range.(8) See Operating Conditions chapter Table 5, IINJ2 parameter. +8 LSB DNL(9) CC P Differential non- linearity Standard frequency mode, VDD_HV_ADV > 4 V VDD_HV_ADR_S > 4 V –1 2 LSB (12b) T High frequency mode, VDD_HV_ADV > 4 V VDD_HV_ADR_S > 4 V –1 2 1. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within the sampling window. Refer to Figure 8 for models of the internal ADC circuit, and the values to use in external RC sizing and calculating the sampling window duration. 2. Mode1: 6 sampling cycles + 10 conversion cycles at 13.33 MHz. 3. Mode2: 5 sampling cycles + 10 conversion cycles at 13.33 MHz. Table 25. SARn ADC electrical specification (continued) Symbol C Parameter Conditions Value Unit Min Max |
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