SPC58EN80C3RMSBY datasheet(70/158 Pages) STMICROELECTRONICS

70 / 158 page

Electrical characteristics

SPC584Nx, SPC58ENx, SPC58NNx

70/158

DS11734 Rev 6

3.12.5

SD ADC filter modes

Table 28 describes the 4 SD ADC filter modes which are controlled by bits BANDSEL, FSEL

and EXTFILTER of the Module Configuration Register (MCR). For details, refer to the

SPC58xNx Reference Manual.

In normal/default mode, modified bandwidth mode and bypass FIR mode, the output values

are not normalized by hardware. To apply normalization by software Table 29 lists the digital

output codes in these modes when input signal is full range.

14. SNR value guaranteed only if external noise on the ADC input pin is attenuated by the required SNR value in the frequency

range of fADCD_M - fADCD_S to fADCD_M + fADCD_S, where fADCD_M is the input sampling frequency, and fADCD_S is the

output sample frequency. A proper external input filter should be used to remove any interfering signals in this frequency

range.

15. The ±1% passband ripple specification is equivalent to 20 * log10 (0.99) = 0.087 dB.

16. For details, refer to Section 3.12.5: SD ADC filter modes.

17. Propagation of the information from the pin to the register CDR[CDATA] and flags SFR[DFEF], SFR[DFFF] is given by the

different modules that need to be crossed: delta/sigma filters, high pass filter, fifo module, clock domain synchronizers. The

time elapsed between data availability at pin and internal S/D module registers is given by the below formula:

of the sampling clock, fADCD_M is the frequency of the modulator, and fPBRIDGEx_CLK is the frequency of the peripheral

bridge clock feeds to the ADC S/D module. The (~+1) symbol refers to the number of clock cycles uncertainty (from 0 to 1

clock cycle) to be added due to resynchronization of the signal during clock domain crossing. Some further latency may be

added by the target module (core, DMA, interrupt) controller to process the data received from the ADC S/D module.

18. This capacitance does not include pin capacitance, that can be considered together with external capacitance, before

sampling switch.

19. Consumption is given after power-up, when steady state is reached. Extra consumption up to 2 mA may be required during

internal circuitry set-up.

Table 28. Filter modes

BANDSEL

FSEL

EXTFILTER

Filter Mode

Normal/Default mode

Modified bandwidth mode

Bypass FIR mode

External filter mode

Table 29. Digital output codes in full scale

OSR

MCR[FSEL] = 1

MCR[GECEN] = 1

MCR[FSEL] = 0

MCR[BANDSEL] = 0

MCR[GECEN] = 1

MCR[FSEL] = 0

MCR[BANDSEL] = 1

MCR[GECEN] = 1

29160

31081

31095

29157

31077

31092

29158

31079

31093

29155

31075

31090

29109

31026

31042

29121

31040

31054

29160

31081

31095

29157

31077

31092

SPC58EN80C3RMSBY データシート(PDF) 70 Page - STMicroelectronics

SPC58EN80C3RMSBY データシート(HTML) 70 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード

リンク URL

SPC58EN80C3RMSBY データシート(PDF) 70 Page - STMicroelectronics

SPC58EN80C3RMSBY データシート(HTML) 70 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシート ダウンロード

リンク URL

データシートダウンロード