SPC58EN80C3RMSBY datasheet(79/158 Pages) STMICROELECTRONICS

79 / 158 page

DS11734 Rev 6

79/158

SPC584Nx, SPC58ENx, SPC58NNx

Electrical characteristics

DCREF

CC D PLL reference clock duty cycle (CLKIN)

—

CC D

Integrated phase noise (single side

band)

fRF_REF = 20 MHz

—

-58

dBc

fVCO

CC P

PLL VCO frequency

—

312

—

320(3) MHz

tLOCK

CC D

PLL phase lock

—

150(4)

µs

ΔPERREF SR

Input reference clock jitter (peak to peak)

Single period,

fRF_REF =20MHz

——

350

Long term,

fRF_REF =20MHz

-500

—

500

ΔPEREYE CC T

Output Eye Jitter (peak to peak)(5)

——

—

400

1. The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces.

2. If the input frequency is lower than 20 MHz, it is required to set a input division factor of 1.

3. The 320 MHz frequency is achieved with a 20 MHz reference clock.

4. The total lock time is the sum of the coarse lock time plus the programmable lock delay time 2 clock cycles of the peripheral

bridge clock that is connected to the PLL on the device (to set the PLL enable bit).

5. Measured at the transmitter output across a 100

Ω termination resistor on a device evaluation board. See Figure 12.

Table 35. LFAST PLL electrical characteristics(1) (continued)

Symbol

Parameter

Conditions

Value

Unit

Min

Typ

Max

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