SPC58EN80C3RMSBY datasheet(11/158 Pages) STMICROELECTRONICS

11 / 158 page

DS11734 Rev 6

11/158

SPC584Nx, SPC58ENx, SPC58NNx

Introduction

1.5

Features

On-chip modules within SPC58xNx include the following features:

•

Three enhanced main CPUs, dual issue, 32-bit CPU core complexes (e200z4256n3),

two of them having a checker core in lock-step.

–

Power Architecture embedded specification compliance

–

Instruction set enhancement allowing variable length encoding (VLE), encoding a

mix of 16-bit and 32-bit instructions, for code size footprint reduction

–

Single-precision floating point operations

–

Lightweight signal processing auxiliary processing unit (LSP APU) instruction

support for digital signal processing (DSP on Core_2)

–

32 KB Local instruction RAM and 128 KB local data RAM for Core_0, Core_1 and

Core_2

–

16 KB I-Cache and 8 KB D-Cache for Core_0, Core_1 and Core_2

•

6582 KB on-chip Flash

–

Supports read during program and erase operations, and multiple blocks allowing

EEPROM emulation

–

Supports read while read between the two code Flash partitions.

•

128 KB on-chip general-purpose SRAM (+ 384 KB data RAM included in the CPUs)

•

Multi channel direct memory access controllers (eDMA paired in lock-step)

–

One eDMA with 64 channels

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One eDMA with 32 channels

•

One interrupt controller (INTC) in lock-step

•

Dual phase-locked loops with stable clock domain for peripherals and FM modulation

domain for computational shell

•

Dual crossbar switch architecture for concurrent access to peripherals, Flash, or RAM

from multiple bus masters with end-to-end ECC

•

Hardware security module (HSM) to provide robust integrity checking of Flash memory

•

System integration unit lite (SIUL)

•

Boot assist Flash (BAF) supports factory programming using a serial bootload through

the asynchronous CAN or LIN/UART.

•

GTM344 - generic timer module

–

Intelligent complex timer module

–

144 channels (48 input and 96 output)

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5 programmable fine grain multi-threaded cores

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61 KB of dedicated RAM

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24-bit wide channels

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Hardware support for engine control, motor control and safety related applications

•

Enhanced analog-to-digital converter system with

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One supervisor 12-bit SAR analog converter

–

Four separate fast 12-bit SAR analog converters

–

Two separate 10-bit SAR analog converters

–

Six separate 16-bit Sigma-Delta analog converters

•

Eight deserial serial peripheral interface (DSPI) modules

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