SPC58EN80C3RMSBY datasheet(26/158 Pages) STMICROELECTRONICS

26 / 158 page

Electrical characteristics

SPC584Nx, SPC58ENx, SPC58NNx

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DS11734 Rev 6

2. The leakage considered is the sum of core logic and RAM memories. The contribution of analog modules is not considered,

and they are computed in the dynamic IDD_LV and IDD_HV parameters.

3. IDD_LKG (leakage current) and IDD_LV (dynamic current) are reported as separate parameters, to give an indication of the

consumption contributors. The tests used in validation, characterization and production are verifying that the total

consumption (leakage+dynamic) is lower or equal to the sum of the maximum values provided (IDD_LKG+IDD_LV). The two

parameters, measured separately, may exceed the maximum reported for each, depending on the operative conditions and

the software profile used.

4. Use case: 3 x e200Z4 @200 MHz with all locksteps on, HSM @100 MHz, all IPs clock enabled, all SARADC and SDADC

in continuous conversion, DMA continuously triggered by ADC conversion, GTM @ 200 MHz (16 TOM channels, 4 ATOM,

4 TIM, DPLL, TBU), 4 CAN / 6 DSPI / PSI5, PLL0-1 running.

5. Dynamic consumption of one core, including the dedicated I/D-caches and I/D-MEMS contribution.

6. Dynamic consumption of the HSM module, including the dedicated memories, during the execution of Electronic Code

Book crypto algorithm on 1 block of 16 byte of shared RAM.

7. Dynamic consumption of the AMU module standalone.

8. Sysclk = RC16 MHz, RC16 MHz ON, RC1 MHz ON, PLL OFF. All possible peripherals off and clock gated. Flash in power

down mode.

9. Worst case usage (data trace, data overlay, full Aurora utilization). If Aurora and JTAGM/LFAST not used, VDD_LV_BD

current is reduced by ~20mA.

10. Current spike may occur during normal operation that are above average current, valid for an application running and if the

following conditions are unchanged: clock configuration, frequency and gating; peripherals activation and configuration;

number of cores and checker-cores activation and configuration; no functional/destructive reset occurring; no mbist/lbist

execution. An internal auxiliary and clamp regulator can be enabled, in order to support internal current variations. Please

refer to the Power Management chapter for the details and the external component requirements.

11. Moving window, measured on application specific pattern, with a maximum of 100 mA for the worst case application.

12. This specification is the maximum value and is a boundary for the dl specification.

13. Condition1: For power on period from 0 V up to normal operation with reset asserted. Condition 2: From reset asserted until

PLL running free. Condition 3: Increasing PLL from free frequency to full frequency. Condition 4: reverse order for power

down to 0 V. Internal schemes must be used by the application (example: frequency ramping feature enable) to ensure that

incremental demands are made on the external power supply within the maximum value. Mbist/Lbist must be configured to

avoid exceeding the maximum value.

14. IDDOFF is the minimum guaranteed consumption of the device during power-up. It can be used to correctly size power-off

ballast in case of current injection during power-off state.

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