SPC58EN80C3RMSBY datasheet(101/158 Pages) STMICROELECTRONICS

101 / 158 page

DS11734 Rev 6

101/158

SPC584Nx, SPC58ENx, SPC58NNx

Electrical characteristics

129

3.18.2.1

DSPI master mode full duplex timing with CMOS and LVDS pads

3.18.2.1.1 DSPI CMOS master mode – classic timing

Note:

In the following table, all output timing is worst case and includes the mismatching of rise

and fall times of the output pads.

Table 51. DSPI channel frequency support

DSPI use mode(1)

Max usable

frequency

(MHz)(2),(3)

CMOS (Master

mode)

Full duplex – Classic timing (Table 52)

DSPI_0, DSPI_3,

DSPI_5, DSPI_6

DSPI_1, DSPI_2,

DSPI_4, DSPI_9

Full duplex – Modified timing (Table 53)

DSPI_0, DSPI_3,

DSPI_5, DSPI_6

DSPI_1, DSPI_2,

DSPI_4, DSPI_9

Output only mode (SCK/SOUT/PCS) (Table 52 and

Table 53) )

—30

Output only mode TSB mode (SCK/SOUT/PCS)

—

LVDS (Master

mode)

Full duplex – Modified timing (Table 54)—

Output only mode TSB mode (SCK/SOUT/PCS)

(Table 55)

—40

CMOS (Slave mode Full duplex) (Table 57)—

1. Each DSPI module can be configured to use different pins for the interface. Refer to the device pinout Microsoft Excel file

attached to the IO_Definition document for the available combinations. It is not possible to reach the maximum

performance with every possible combination of pins.

2. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.

3. Maximum usable frequency does not take into account external device propagation delay.

Table 52. DSPI CMOS master classic timing (full duplex and output only)

MTFE = 0, CPHA = 0 or 1

Symbol

C Characteristic

Condition

Value(1)

Unit

Pad drive(2)

Load (CL)Min

Max

1tSCK

CC D SCK cycle time

SCK drive strength

Very strong

25 pF

59.0

—

Strong

50 pF

80.0

—

Medium

50 pF

200.0

—

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