MCP3901A2T-ISLASHSS datasheet(37/60 Pages) MICROCHIP

37 / 60 page

DS22192A-page 37

MCP3901

6.9

Data Ready Pin (DR)

To signify when channel data is ready for transmission,

the data ready signal is available on the data ready pin

(DR) through an active low pulse at the end of a

channel conversion.

The data ready pin outputs an active low pulse with a

period is equal to DRCLK clock period and with a width

equal to one DMCLK period.

When not active low, this pin can either be in high

impedance (when DR_HIZN=0) or in a defined logic

high state (when DR_HIZN=1). This is controlled

through the configuration registers. This allows multiple

devices to share the same data ready pin (with a

pull-up resistor connected between DR and DVDD) in

3-phase

energy

meter

designs

reduce

microcontroller pin count. A single device on the bus

does not require a pull-up resistor.

After a data ready pulse has occurred, the ADC output

data can be read through SPI communication. Two sets

of latches at the output of the ADC prevent the

communication from outputting corrupted data (see

Section 6.10 “Data Ready Latches And Data Ready

Modes (DRMODE<1:0>)”).

The CS pin has no effect on the DR pin, which means

even if CS is high, data ready pulses will be provided

(except

when

the

configuration

prevents

from

outputting data ready pulses). The DR pin can be used

as an interrupt when connected to a MCU or DSP.

While RESET pin is low, the DR pin is not active.

6.10

Data Ready Latches And Data

Ready Modes (DRMODE<1:0>)

To ensure that both channel ADC data are present at

the same time for SPI read, regardless of phase delay

settings for either or both channels, there are two sets

of latches in series with both the data ready and the

‘read start’ triggers.

The first set of latches holds each output when data is

ready and latches both outputs together when

DRMODE<1:0>=00. When this mode is on, both ADCs

work together and produce one set of available data

after each data ready pulse (that corresponds to the

lagging ADC data ready). The second set of latches

ensures that when reading starts on an ADC output, the

corresponding data is latched so that no data

corruption can occur.

If an ADC read has started, in order to read the

following ADC output, the current reading needs to be

completed (all bits must be read from the ADC output

data registers).

6.10.1

DATA READY PIN (DR) CONTROL

USING DRMODE BITS

There are four modes that control the data ready

pulses,

and

these

modes

are

set

with

the

DRMODE<1:0> bits in the STATUS/COM register. For

power metering applications, DRMODE<1:0>=00 is

recommended (default mode).

The position of DR pulses vary with respect to this

mode, to the OSR and to the PHASE settings:

• DRMODE<1:0> = 11: Both Data Ready pulses

from ADC Channel 0 and ADC Channel 1 are

output on DR pin.

• DRMODE<1:0> = 10: Data Ready pulses from

ADC Channel 1 are output on DR pin. DR from

ADC Channel 0 are not present on the pin.

• DRMODE<1:0> = 01: Data Ready pulses from

ADC Channel 0 are output on DR pin. DR from

ADC Channel 1 are not present on the pin.

• DRMODE<1:0> = 00: (Recommended, and

Default Mode). Data Ready pulses from the

lagging ADC between the two are output on DR

pin. The lagging ADC depends on the phase

ADCs are linked together so their data is latched

together when the lagging ADC output is ready.

MCP3901A2T-I/SS データシート(PDF) 37 Page - Microchip Technology

MCP3901A2T-I/SS データシート(HTML) 37 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

データシートダウンロード