MCP3901A2T-ISLASHSS datasheet(47/60 Pages) MICROCHIP

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DS22192A-page 47

MCP3901

STATUS AND COMMUNICATION REGISTER -> ADDRESS 0X09

R/W-1

R/W-0

R/W-1

R/W-0

R-1

READ<1>

READ<0>

DR_LTY

DR_HIZN

DRMODE<1> DRMODE<0> DRSTATUS_

CH1

DRSTATUS_

CH0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7:6

READ: Address Loop Setting

= Address counter loops on entire register map

= Address counter loops on register TYPES (DEFAULT)

= Address counter loops on register GROUPS

= Address not incremented, continually read same single register

bit 5

DR_LTY: Data Ready Latency Control

= “No Latency” Conversion, DR pulses after 3 DRCLK periods. (Default)

= Unsettled Data is available after every DRCLK period

bit 4

DR_HIZn: Data Ready Pin Inactive State Control

= The data ready pin default state is a logic high when data is NOT ready

= The data ready pin default state is high impedance when data is NOT ready (Default)

bit 3:2

DRMODE<1:0>: Data Ready Pin (DR) control

= Both Data Ready pulses from ADC0 and ADC Channel 1 are output on the DR pin.

= Data Ready pulses from ADC Channel 1 are output on the DR pin. DR from ADC Channel 0 are

not present on the pin.

= Data Ready pulses from ADC Channel 0 are output on the DR pin. DR from ADC Channel 1 are

not present on the pin.

= Data Ready pulses from the lagging ADC between the two are output on the DR pin. The lagging

ADC selection depends on the phase register and on the OSR (default).

bit 1:0

DRSTATUS<1:0>: Data Ready Status

= ADC Channel 1 and Channel 0 data not ready (Default)

= ADC Channel 1 data not ready, ADC Channel 0 data ready

= ADC Channel 0 data not ready, ADC Channel 1 data ready

= ADC Channel 1 and Channel 0 data ready

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