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MCP3901A2T-I/SS データシート(PDF) 48 Page - Microchip Technology |
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MCP3901A2T-I/SS データシート(HTML) 48 Page - Microchip Technology |
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48 / 60 page ![]() MCP3901 DS22192A-page 48 © 2009 Microchip Technology Inc. 7.6 Configuration Registers The configuration registers contain settings for the internal clock prescaler, the oversampling ratio, the channel 0 and channel 1 width settings of 16 or 24 bits, the modulator output control settings, the state of the channel resets and shutdowns, the dithering algorithm control (for idle tones suppression), and the control bits for the external VREF and external CLK. REGISTER 7-6: CONFIGURATION REGISTERS: CONFIG1: ADDRESS 0X0A, CONFIG2: ADDRESS 0X0B R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PRESCALE <1> PRESCALE <0> OSR<1> OSR<0> WIDTH _CH1 WIDTH _CH0 MODOUT _CH1 MODOUT _CH0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 RESET _CH1 RESET _CH0 SHUTDOWN _CH1 SHUTDOWN _CH0 DITHER _CH1 DITHER _CH0 VREFEXT CLKEXT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15:14 PRESCALE<1:0> Internal Master Clock (AMCLK) Prescaler Value 11 = AMCLK = MCLK/ 8 10 = AMCLK = MCLK/ 4 01 = AMCLK = MCLK / 2 00 = AMCLK = MCLK (default) bit 13-12 OSR<1:0> Oversampling Ratio for Delta-Sigma A/D Conversion (all channels, DMCLK/DRCLK) 11 = 256 10 = 128 01 = 64 (default) 00 = 32 bit 11:10 WIDTH<1:0> ADC Channel output data word width 1 = 24 bit mode 0 = 16 bit mode(default) bit 9:8 MODOUT<1:0>: Modulator Output Setting for MDAT pins 11 = Both CH0 and CH1 Modulator Outputs present on MDAT1 and MDAT0 pins 10 = CH1 ADC Modulator Output present on MDAT1 pin 01 = CH0 ADC Modulator Output present on MDAT0 pin 00 = No modulator output is enabled (default) bit 7:6 RESET<1:0>: RESET MODE SETTING FOR ADCs 11 = Both CH0 and CH1 ADC are in reset mode 10 = CH1 ADC in reset mode 01 = CH0 ADC in reset mode 00 = Neither Channel in reset mode(default) bit 5:4 SHUTDOWN<1:0>: SHUTDOWN MODE SETTING FOR ADCs 11 = Both CH0 and CH1 ADC in Shutdown 10 = CH1ADC in Shutdown 01 = CH0 ADC in Shutdown 00 = Neither Channel in Shutdown(default) bit 3:2 DITHER<1:0>: Control for dithering circuit 11 = Both CH0 and CH1 ADC have dithering circuit applied (default) 10 = Only CH1 ADC has dithering circuit applied 01 = Only CH0 ADC has dithering circuit applied 00 = Neither Channel has dithering circuit applied |
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