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PM0056 データシート(PDF) 62 Page - STMicroelectronics |
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PM0056 データシート(HTML) 62 Page - STMicroelectronics |
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62 / 156 page  The Cortex-M3 instruction set PM0056 62/156 DocID15491 Rev 5 Operation LDR instructions load one or two registers with a value from memory. STR instructions store one or two register values to memory. Load and store instructions with immediate offset can use the following addressing modes: • Offset addressing The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access. The register Rn is unaltered. The assembly language syntax for this mode is: [Rn, #offset]. • Pre-indexed addressing The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the address for the memory access and written back into the register Rn. The assembly language syntax for this mode is: [Rn, #offset]! • Post-indexed addressing The address obtained from the register Rn is used as the address for the memory access. The offset value is added to or subtracted from the address, and written back into the register Rn. The assembly language syntax for this mode is: [Rn], #offset. The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either be signed or unsigned (see Address alignment on page 56). Table 25 shows the range of offsets for immediate, pre-indexed and post-indexed forms. Restrictions • For load instructions – Rt can be SP or PC for word loads only – Rt must be different from Rt2 for two-word loads – Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms • When Rt is PC in a word load instruction – bit[0] of the loaded value must be 1 for correct execution – A branch occurs to the address created by changing bit[0] of the loaded value to 0 – If the instruction is conditional, it must be the last instruction in the IT block • For store instructions – Rt can be SP for word stores only – Rt must not be PC – Rn must not be PC – Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms Table 25. Immediate, pre-indexed and post-indexed offset ranges Instruction type Immediate offset Pre-indexed Post-indexed Word, halfword, signed halfword, byte, or signed byte -255 to 4095 -255 to 255 -255 to 255 Two words Multiple of 4 in the range -1020 to 1020 Multiple of 4 in the range -1020 to 1020 Multiple of 4 in the range -1020 to 1020 |
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