PM0056 datasheet(66/156 Pages) STMICROELECTRONICS

66 / 156 page

The Cortex-M3 instruction set

PM0056

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DocID15491 Rev 5

Operation

LDR loads a register with a value from a PC-relative memory address. The memory address

is specified by a label or by an offset from the PC.

The value to load or store can be a byte, halfword, or word. For load instructions, bytes and

halfwords can either be signed or unsigned (see Address alignment on page 56).

‘label’ must be within a limited range of the current instruction. Table 26 shows the possible

offsets between label and the PC.

You might have to use the .W suffix to get the maximum offset range (see Instruction width

selection on page 59).

Restrictions

In these instructions:

•

Rt can be SP or PC only for word loads

•

Rt2 must be neither SP nor PC

•

Rt must be different from Rt2

When Rt is PC in a word load instruction:

•

bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this

halfword-aligned address

•

If the instruction is conditional, it must be the last instruction in the IT block.

Condition flags

These instructions do not change the flags.

Examples

LDRR0, LookUpTable; load R0 with a word of data from an address

; labelled as LookUpTable

LDRSBR7, localdata; load a byte value from an address labelled

; as localdata, sign extend it to a word

; value, and put it in R7

Table 26. label-PC offset ranges

Instruction type

Offset range

Word, halfword, signed halfword, byte, signed byte

−4095 to 4095

Two words

−1020 to 1020

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