L9908_V01 datasheet(132/152 Pages) STMICROELECTRONICS

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The refresh of the overflow counter has to be performed by the uC through a dedicated SPI frame including the 4-

bit watchdog refresh command. The watchdog circuitry compares the received watchdog refresh command with

an internal look-up table and answers with a corresponding 4-bit Gray code in the next SPI MISO frame.

Table 148. Watchdog binary to Gray answer conversion

Binary (μC) → Gray (L9908) Binary → (μC) → Gray (L9908) Binary (μC) → Gray (L9908) Binary (μC) → Gray (L9908)

0x0 (0000) → 0x0 (0000)

0x4 (0100) → 0x6 (0110)

0x8 (1000) → 0xC (1100)

0xC (1100) → 0xA (1010)

0x1 (0001) → 0x1 (0001)

0x5 (0101) → 0x7 (0111)

0x9 (1001) → 0xD (1101)

0xD (1101) → 0xB (1011)

0x2 (0010) → 0x3 (0011)

0x6 (0110) → 0x5 (0101)

0xA (1010) → 0xF (1111)

0xE (1110) → 0x9 (1001)

0x3 (0011) → 0x2 (0010)

0x7 (0111) → 0x4 (0100)

0xB (1011) → 0xE (1110)

0xF (1111) → 0x8 (1000)

The expected watchdog command order starts with the number 0x0 (0000) and is incremented by 1 at each

refresh window if the command is correctly interpreted and no failure is detected.

Once command number 0xF (1111) is reached the sequence restarts with number 0x0 (0000).

Figure 87. Watchdog command order sequence

In case of a wrong WDT data command (command different from the expected sequence order), the watchdog

word fail counter is incremented by 1. With the next valid watchdog data command the fail counter is decreased

by 1. If the failure counter reaches the failure limit defined in the SPI register WDT_FAIL_COUNT_CFG the

watchdog fail flag WDT_DATA_fail is set and L9908 is sent to safe state.

The fail counter limit can be programmed by the following SPI bit set:

Table 149. Watchdog configuration table for WDT data fail counter

WDT_FAIL_COUNT_CFG1

WDT_FAIL_COUNT_CFG0

Description

3 (Default)

L9908

Functional description

DS13546 - Rev 5

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