MAC7200 datasheet(43/976 Pages) FREESCALE

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MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

xliii

11-51

A7S Nexus3 DMA clock relationships................................................................................189

11-52

Debug Status Message Format.............................................................................................189

11-53

JTAG State Machine............................................................................................................190

12-1

DMA Block Diagram...........................................................................................................201

12-2

DMA Control Register (DMACR) ......................................................................................210

12-3

DMA Error Status (DMAES) Register ................................................................................211

12-4

DMA Enable Request (DMAERQH, DMAERQL) Register ..............................................213

12-5

DMA Enable Error Interrupt (DMAEEIH, DMAEEIL) Registers......................................214

12-6

DMA Set Enable Request (DMASERQ) Register...............................................................215

12-7

DMA Clear Enable Request (DMACERQ) Register...........................................................216

12-8

DMA Set Enable Error Interrupt (DMASEEI) Register......................................................216

12-9

DMA Clear Enable Error Interrupt (DMACEEI) Register..................................................217

12-10

DMA Clear Interrupt Request (DMACINT) Register .........................................................217

12-11

DMA Clear Error (DMACERR) Register ...........................................................................218

12-12

DMA Set START Bit (DMASSRT) Register......................................................................219

12-13

DMA Clear DONE Status (DMACDNE) Register .............................................................219

12-14

DMA Interrupt Request (DMAINTH, DMAINTL) Registers ............................................220

12-15

DMA Error (DMAERRH, DMAERRL) Registers..............................................................222

12-16

DMA Channel n Priority (DCHPRIn) Register ...................................................................223

12-17

TCDn Word 0 (TCDn.saddr) Field ......................................................................................224

12-18

TCDn Word 1 (TCDn.{soff,smod,ssize,dmod,dsize}) Fields .............................................225

12-19

TCDn Word 2 (TCDn.nbytes) Field ....................................................................................226

12-20

TCDn Word 3 (TCDn.slast) Field .......................................................................................227

12-21

TCDn Word 4 (TCDn.daddr) Field .....................................................................................227

12-22

TCDn Word 5 (TCDn.{citer,doff}) Fields ..........................................................................228

12-23

TCDn Word 6 (TCDn.dlast_sga) Field................................................................................229

12-24

TCDn Word 7 (TCDn.{biter,control/status}) Fields ...........................................................230

12-25

ipd_req removal ...................................................................................................................242

13-1

Processor Core Type (PCT) Register...................................................................................245

13-2

Revision (REV) Register .....................................................................................................246

13-3

AXBS Master Configuration (AMC) Register ....................................................................246

13-4

AXBS Slave Configuration (ASC) Register........................................................................247

13-5

IPS Module Configuration (IMC) Register .........................................................................248

13-6

Miscellaneous Reset Status (MRSR) Register.....................................................................248

13-7

Miscellaneous Wakeup Control (MWCR) Register ............................................................249

13-8

Miscellaneous Software Watchdog Timer Control (MSWTCR) Register ..........................251

13-9

Miscellaneous Software Watchdog Timer Service (MSWTSR) Register ...........................253

13-10

Miscellaneous Interrupt (MIR) Register ..............................................................................253

13-11

AXBS Address Map (AAMR) Register ..............................................................................254

13-12

Miscellaneous User-Defined Control (MUDCR) Register..................................................255

13-13

NMI Control (NMICR) Register .........................................................................................256

13-14

Non-Maskable Interrupt Operation Timing .........................................................................257

13-15

Peripheral Power Management Set (PPMRS) Register .......................................................258

13-16

Peripheral Power Management Clear (PPMRC) Register ...................................................258

13-17

Peripheral Power Management Set 1 (PPMRS1) Register ..................................................259

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