MAC7200 datasheet(59/976 Pages) FREESCALE

59 / 976 page

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

lix

25-2

STATUS Allowed Register Accesses..................................................................................451

25-3

STATUS Field Descriptions ................................................................................................451

25-4

MEMCONFIG Field Descriptions.......................................................................................453

25-5

MEMCONFIG Allowed Register Accesses ........................................................................453

25-6

DEBUGPORT Field Descriptions .......................................................................................454

25-7

Debug Status Port Modes.....................................................................................................454

25-8

DEBUGPORT Allowed Register Accesses.........................................................................455

25-9

ERROR Field Descriptions..................................................................................................456

25-10

ERROR Allowed Register Accesses ...................................................................................456

25-11

SYSRESET Field Descriptions............................................................................................457

25-12

SYSRESET Allowed Register Accesses .............................................................................457

25-13

SSM Bus Aborts ..................................................................................................................459

26-1

PIT Timer Usage..................................................................................................................463

26-2

PIT Bus Aborts ....................................................................................................................464

26-3

PIT Interrupt Sources ...........................................................................................................464

26-4

PIT_RTI Memory Map ........................................................................................................465

26-5

TLVAL0 Field Descriptions ................................................................................................467

26-6

TLVAL1–10 Field Descriptions ..........................................................................................468

26-7

TVAL0 Field Descriptions ..................................................................................................469

26-8

TVAL1–10 Field Descriptions ............................................................................................470

26-9

PITFLG Field Desciptions ...................................................................................................471

26-10

PITINTEN Field Descriptions .............................................................................................472

26-11

PITINTSEL Field Descriptions ...........................................................................................473

26-12

PITEN Field Descriptions....................................................................................................474

26-13

PITCTRL Field Descriptions ...............................................................................................475

26-14

PIT Interrupt Vectors ...........................................................................................................477

27-1

DMA Request Sources.........................................................................................................481

27-2

Module Memory Map ..........................................................................................................483

27-3

CHCONFIGxx Field Descriptions.......................................................................................484

27-4

Channel and Trigger Enabling .............................................................................................484

27-5

SOURCE Configuration ......................................................................................................484

27-6

DMA Channel Mux Bus Aborts ..........................................................................................490

27-7

MAC71xx versus MAC72xx DMA Channel Mux Assignment..........................................490

28-1

CAN External Pins...............................................................................................................503

28-2

FlexCAN Memory Map .......................................................................................................504

28-3

FlexCAN Signals .................................................................................................................509

28-4

Module Memory Map ..........................................................................................................510

28-5

Message Buffer MB0 Memory Mapping.............................................................................511

28-6

Message Buffer Field Descriptions......................................................................................512

28-7

Message Buffer Code for Rx buffers ...................................................................................513

28-8

Message Buffer Code for Tx buffers ...................................................................................513

28-9

MCR Field Descriptions ......................................................................................................515

28-10

CTRL Field Descriptions .....................................................................................................518

28-11

RXGMASK Field Descriptions ...........................................................................................522

28-12

ESR Field Descriptions........................................................................................................524

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