MAC7200 datasheet(44/976 Pages) FREESCALE

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MAC7200 Microcontroller Family Reference Manual, Rev. 2

xliv

Freescale Semiconductor

13-18

Peripheral Power Management Clear 1 (PPMRC1) Register ..............................................259

13-19

Peripheral Power Management Register High (PPMRH) ...................................................260

13-20

Peripheral Power Management Register Low (PPMRL).....................................................261

13-21

Peripheral Power Management Register 1 High (PPMR1H) ..............................................262

13-22

Peripheral Power Management Register 1 Low (PPMR1L)................................................262

13-23

ECC Configuration (ECR) Register.....................................................................................264

13-24

ECC Status (ESR) Register..................................................................................................265

13-25

ECC Error Generation (EEGR) Register .............................................................................267

13-26

Flash ECC Address (FEAR) Register..................................................................................270

13-27

Flash ECC Master Number (FEMR) Register .....................................................................270

13-28

Flash ECC Attributes (FEAT) Register ...............................................................................271

13-29

Flash ECC Data (FEDR) Register .......................................................................................272

13-30

Platform Flash ECC Data (PFEDR) Register ......................................................................272

13-31

RAM ECC Address (REAR) Register .................................................................................273

13-32

RAM ECC Syndrome (RESR) Register ..............................................................................273

13-33

RAM ECC Master Number (REMR) Register ....................................................................275

13-34

RAM ECC Attributes (REAT) Register ..............................................................................275

13-35

RAM ECC Data (REDR) Register ......................................................................................277

13-36

Core Fault Address (CFADR) Register ...............................................................................278

13-37

Core Fault Location 1 (CFLOC1) Register .........................................................................278

13-38

Core Fault Location (CFLOC) Register ..............................................................................279

13-39

Core Fault Attributes (CFATR) Register.............................................................................279

13-40

Core Fault Data (CFDTR) Register .....................................................................................281

14-1

INTC Block Diagram...........................................................................................................291

14-2

Interrupt Pending (IPRH, IPRL) Registers ..........................................................................295

14-3

Interrupt Mask (IMRH, IMRL) Registers............................................................................297

14-4

Force Interrupt (INTFRCH, INTFRCL) Registers ..............................................................298

14-5

Interrupt Configuration (ICONFIG) Register ......................................................................299

14-6

Set Interrupt Mask (SIMR) Register....................................................................................301

14-7

Clear Interrupt Mask (CIMR) Register................................................................................301

14-8

Current Level Mask (CLMASK) Register...........................................................................302

14-9

Saved Level Mask (SLMASK) Register..............................................................................303

14-10

Interrupt Control Register n (ICRn).....................................................................................304

14-11

IRQ Interrupt Acknowledge Register (IRQIACK)..............................................................305

14-12

FIQ Interrupt Acknowledge Register (FIQIACK)...............................................................306

14-13

Interrupt Service Routine and Masking (Not To Scale) ......................................................311

15-1

Crossbar Switch Bus Block Diagram ..................................................................................313

16-1

AIPS Interface Block Diagram ............................................................................................324

16-2

AIPS Memory Map..............................................................................................................325

16-3

Master Protection Registers (MPROT)................................................................................331

16-4

Peripheral Access Control Registers (PACR)......................................................................332

17-1

FlexBus Controller Conceptual Diagram

(Non-Muxed Implementation) .........................................................................................340

17-2

Chip-Select Address Registers (CSARn).............................................................................345

17-3

Chip-Select Mask Registers (CSMRn) ................................................................................346

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