MAC7200 datasheet(20/976 Pages) FREESCALE

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MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

18.7.4.1

Flash Block User Registers......................................................................................363

18.7.4.1.1

PFCR1 - PFLASH Configuration Register 1 ......................................................364

18.7.4.1.2

PFAPR - PFLASH Access Protection Register ...................................................366

18.7.4.1.3

PFCR2 - PFLASH Configuration Register 2 ......................................................367

18.7.4.1.4

PFSACC - PFLASH Supervisor/user ACCess ....................................................367

18.7.4.1.5

PFDACC - PFLASH Data/instruction ACCess...................................................367

18.7.4.2

Flash MCM Registers ..............................................................................................368

18.7.4.2.1

PFWACC - PFLASH Write ACCess ...................................................................368

18.7.5

Flash Access Protection ...............................................................................................368

18.7.6

Flash Program/Erase Protection and Selection............................................................372

18.7.7

Flash Programming Word Size ....................................................................................374

18.7.8

Read-while-Write (RWW) ...........................................................................................374

18.7.9

Flash Security ..............................................................................................................374

18.7.9.1

Securing the device..................................................................................................374

18.7.9.2

Unsecuring the device..............................................................................................375

18.7.10

Flash Timing ................................................................................................................375

Chapter 19 SRAM and SRAM Controller

19.1

SRAM ..............................................................................................................................377

19.1.1

SRAM Features............................................................................................................377

19.1.2

SRAM Protocol............................................................................................................377

19.1.3

SRAM External Pins....................................................................................................377

19.1.4

SRAM Bus Aborts .......................................................................................................377

19.1.5

SRAM Differences from MAC71xx............................................................................377

19.1.6

SRAM Application Usage ...........................................................................................378

19.1.6.1

SRAM Initialization.................................................................................................378

19.1.6.2

SRAM Address Mirroring .......................................................................................378

19.2

Platform RAM Array Controller (PRAM_CTL) .............................................................378

19.2.1

Introduction..................................................................................................................378

19.2.2

PRAM_CTL Interface Description..............................................................................381

19.2.2.1

Overview..................................................................................................................381

19.2.2.2

Detailed Signal Descriptions ...................................................................................382

19.2.3

Functional Description.................................................................................................385

19.2.3.1

Error Correcting Code (ECC)..................................................................................385

19.2.3.1.1

Overview .............................................................................................................385

19.2.3.2

Max Address ............................................................................................................387

19.2.3.3

Read / Write Introduction ........................................................................................387

19.2.3.4

Reads........................................................................................................................388

19.2.3.4.1

Unaligned Reads..................................................................................................388

19.2.3.5

Writes.......................................................................................................................388

19.2.3.5.1

32-bit / 64-bit Writes............................................................................................388

19.2.3.5.2

Less than 32-bit Writes ........................................................................................390

19.2.3.5.3

Unaligned Writes .................................................................................................391

19.2.3.6

Late Write Hits.........................................................................................................392

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