MAC7200 datasheet(16/976 Pages) FREESCALE

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MAC7200 Microcontroller Family Reference Manual, Rev. 2

xvi

Freescale Semiconductor

13.3.2.4

Misc. Reset Status Register (MRSR).......................................................................283

13.3.2.5

Misc. Wakeup Control Register (MWCR) ..............................................................283

13.3.2.6

Software Watchdog Timer (SWT) ...........................................................................283

13.3.2.7

AXBS Address Map Register (AAMR) ..................................................................284

13.3.2.8

Misc. User-Defined Control Register (MUDCR)....................................................284

13.3.2.9

ECC..........................................................................................................................284

13.3.2.10

Fault Registers .........................................................................................................284

13.3.2.11

Non-Maskable Interrupt (NMI) ...............................................................................284

13.3.3

MCM External Pins .....................................................................................................284

13.3.4

MCM Bus Aborts.........................................................................................................284

13.3.5

MCM Differences from MAC71xx .............................................................................285

13.3.6

MCM Application Usage.............................................................................................286

13.3.6.1

Enabling the MCM ..................................................................................................286

13.3.6.2

ECC..........................................................................................................................286

13.3.6.3

Flash.........................................................................................................................286

13.3.6.4

AAMR .....................................................................................................................286

13.3.6.5

NMI..........................................................................................................................286

13.3.6.6

REV Register ...........................................................................................................286

Chapter 14

SPP Interrupt Controller Module for ARM (SPP_INTC_ARM)

14.1

Introduction......................................................................................................................287

14.1.1

Overview......................................................................................................................287

14.2

INTC Features..................................................................................................................287

14.3

INTC External Pins..........................................................................................................288

14.4

INTC Bus Aborts .............................................................................................................288

14.5

INTC Differences from MAC71xx..................................................................................288

14.6

INTC Application Usage .................................................................................................289

14.6.1

Enabling the INTC.......................................................................................................290

14.7

The Interrupt Controller Module (INTC) ........................................................................290

14.7.1

Review of ARM Interrupt Architecture.......................................................................291

14.8

Memory Map/Register Definition ...................................................................................292

14.8.1

Register Descriptions...................................................................................................294

14.8.1.1

IPR[63:0] - Interrupt Pending Register (IPRH, IPRL) ............................................294

14.8.1.2

IMR[63:0] - Interrupt Mask Register (IMRH, IMRL) ............................................296

14.8.1.3

INTFRC[63:0] - Force Interrupt Register (INTFRCH, INTFRCL) ........................297

14.8.1.4

Interrupt Configuration (ICONFIG) Register..........................................................299

14.8.1.5

Set Interrupt Mask (SIMR) Register........................................................................300

14.8.1.6

Clear Interrupt Mask (CIMR) Register....................................................................301

14.8.1.7

Current Level Mask (CLMASK) Register ..............................................................302

14.8.1.8

Saved Level Mask (SLMASK) Register .................................................................303

14.8.1.9

Interrupt Control Register n (ICRn), n = 0, 1, 2,..., 63 ............................................304

14.8.1.10

IRQ Interrupt Acknowledge Register (IRQIACK)..................................................304

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