MAC7200 datasheet(49/976 Pages) FREESCALE

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MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

xlix

32-17

Input Pulse Width Measurement example ...........................................................................703

32-18

B1 and A1 updates at UCAn and UCBn reads ....................................................................703

32-19

Input Period Measurement example ....................................................................................704

32-20

A1 and B1 updates at UCAn and UCBn reads ....................................................................705

32-21

Double Action Output Compare with FLAG set on the second match ...............................706

32-22

Double Action Output Compare with FLAG set on both matches ......................................706

32-23

Pulse/Edge Accumulation continuous mode example .........................................................707

32-24

Pulse/Edge Accumulation single-shot mode example .........................................................708

32-25

Pulse/Edge Counting continuous mode example.................................................................709

32-26

Pulse/Edge Counting single-shot mode example.................................................................709

32-27

Quadrature Decode mode example with count & direction encoder ...................................710

32-28

Quadrature Decode mode example with phase_a & phase_B encoder ...............................710

32-29

Windowed Programmable Time Accumulation example....................................................711

32-30

Modulus Counter up mode example ....................................................................................712

32-31

Modulus Counter up/down mode example ..........................................................................712

32-32

Modulus Counter Buffered (MCB) Up Count mode ...........................................................713

32-33

Modulus Counter Buffered (MCB) Up/Down Mode...........................................................714

32-34

MCB Mode A1 Register Update in Up Counter Mode .......................................................714

32-35

MCB Mode A1 Register Update in Up/Down Counter Mode ............................................715

32-36

OPWFM with immediate update .........................................................................................716

32-37

OPWFM with next period update ........................................................................................716

32-38

OPWFMB A1 and B1 match to Output Register Delay ......................................................717

32-39

OPWFMB Mode with A1 = 0 (0% duty cycle) ...................................................................718

32-40

OPWFMB A1 and B1 Registers Update and Flags .............................................................719

32-41

OPWFMB Mode with Active Output Disable.....................................................................719

32-42

OPWFMB Mode from 100% to 0% Duty Cycle .................................................................720

32-43

Output PWMC with leading dead time insertion.................................................................722

32-44

Output PWMC with trailing dead time insertion .................................................................722

32-45

OPWMCB A1 and B1 registers load ...................................................................................723

32-46

Output PWMCB with Lead Dead Time Insertion ...............................................................724

32-47

Output PWMCB with Trail Dead Time Insertion................................................................725

32-48

OPWMCB with 100% Duty Cycle (A1=4 and B1=3) ........................................................727

32-49

Output PWM with immediate update ..................................................................................728

32-50

Output PWM with next period update .................................................................................729

32-51

OPWMB Mode Matches and Flags .....................................................................................730

32-52

OPWMB Mode with 0% Duty Cycle ..................................................................................731

32-53

OPWMB Mode with Active Output Disable .......................................................................732

32-54

OPWMB Mode from 100% to 0% Duty Cycle ...................................................................732

32-55

lnput Programmable Filter submodule diagram ..................................................................733

32-56

Input Programmable filter example .....................................................................................733

32-57

Time base period when running in the fastest pre scaler ratio.............................................735

32-58

Time base period when running with a pre scaler ratio greater than 1 ................................736

33-1

DMADC1032 Block Diagram .............................................................................................742

33-2

ATD Trigger Control Register (ATDTRIGCTL) ................................................................747

33-3

ATD External Trigger Channel Register (ATDETRIGCH) ................................................748

MAC7200 データシート(PDF) 49 Page - Freescale Semiconductor, Inc

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