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MAC7200 データシート(PDF) 87 Page - Freescale Semiconductor, Inc

部品番号 MAC7200
部品情報  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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メーカー  FREESCALE [Freescale Semiconductor, Inc]
ホームページ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 データシート(HTML) 87 Page - Freescale Semiconductor, Inc

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Modes of Operation
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
9
1.3
Modes of Operation
This section describes the various functional modes of the MAC72xx devices. A functional mode is
selected by asserting the MODA and MODB pins (PD1 and PD0, respectively) while the RESET pin is
asserted. Because there is no way to determine when these values are latched inside the device, the
MODA/MODB pins must be asserted the entire time that the RESET pin is asserted. External (weak)
pull-ups and/or pull-downs may be used for this purpose. Table 1-3 shows the values of the
MODA/MODB pins for each chip mode. Note that these encodings are only valid when the TEST pin is
negated (tied low).
Once a chip mode has been set, it may only be changed by any of the following:
Securing the flash, and resetting the device. In this case the mode changes from “XXX Unsecured
Mode” to “XXX Secured Mode”.
Unsecuring the flash, and resetting the device. In this case the mode changes from “XXX Secured
Mode” to “XXX Unsecured Mode”.
Changing the MODA/MODB pins and resetting the device. In this case the mode changes from
“XXX Secured/Unsecured Mode” to “YYY Secured/Unsecured Mode”.
Table 1-2. Typical System Access Summary
Port
Typical
(cycles)
Purpose
Comments
ARM7 Core
Flash
(Port M0=>S0)1
1. Port notations refer to Crossbar ports, and are explained in Chapter 15, “MAC7200
Crossbar Switch (AXBS)”.
RD: 1.2
(per instr.)
WR: N/A
Instruction Fetch
SRAM2
(Port M0=>S3)1
2. Assumes 0 programmed wait-states.
RD: 1
WR: 1
Operand
Read/Write
External Bus
(Port M0=>S1)1
RD: 2
WR: 2
Operand
Read/Write
Peripheral Bus Periphs
(Port M0=>S2)1
RD: 3
WR: 4
Peripheral
Config
DMA
Flash
(Port M1=>S0)1
RD: 3
WR: 4
Program Flash
SRAM2
(Port M1=>S3)1
RD: 1
WR: 1
Periph to/from
SRAM
External Bus
(Port M1=>S1)1
RD: 2
WR: 2
Periph to/from Ext.
Memory
Peripheral Bus Periphs
(Port M1=>S2)1
RD: 3
WR: 4
Periph to/from
SRAM



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