MAC7200 datasheet(68/976 Pages) FREESCALE

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Terminology

MAC7200 Microcontroller Family Reference Manual, Rev. 2

lxviii

Freescale Semiconductor

CRG

Clock and Reset Generator module

Chip Select. In Master Mode, the CS signal is used to select which slave device to talk to.

CSI

Combined Serial Interface. DSPI configuration that alternates DSI and SPI frames.

CSM

Conversion state machine

DAC

Digital to Analog Converter: Converts a binary value into a voltage

DAIC

Double Action Input Capture

DAOC

Double Action Output Compare

Debug Mode

This is a system mode intended for debugging operations. When this mode is triggered, a

global Debug Mode Request signal is sent to all modules, so that they can prepare themselves

with debugging capabilities.

Deserialize

To convert data from a serial format to a parallel format.

DMA

Direct memory access

DMA Mux

Direct Memory Access Multiplexer module

DMADC1032

ATD with DMA interface

Dominant Bit

A dominant bit wins the arbitration on the CAN bus. It is transmitted as ‘0.’

Doze Mode

This is a system low power mode in which the CPU bus is kept alive and a global Doze Mode

request is sent to all peripherals asking them to enter low power mode. Typically, when Doze

Mode is requested, each peripheral can be enabled individually to enter or not low power

mode.

Drain

To remove entries from a FIFO by software or hardware.

DSI

Deserial Serial Interface. DSPI configuration that serializes and deserializes registers or

purpleline signals to allow for pin reduction.

DSI Frame

Collection of serialized or deserialized pin states or register bits transferred over the serial link

DSPI

(Deserialized) Serial Peripheral Interface

ECC

Error Correction Code. Internally used to correct single bit errors, or detect double errors within

a 64 bit double word.

ECLK

E clock

eDMA

Enhanced Direct Memory Access controller module

EmbeddedICE

The ARM7 EmbeddedICE debug module. This module integrated with each ARM7 core

provides all static (core halted) debug functionality. This module is compliant with Class1 of the

IEEE-ISTO 5001 standard.

eMIOS

Enhanced Modular Input/Output Subsystem

EOQ

End of Queue

Erase State

Flash array bit state that reads as a “1.”

eSCI

Enhanced SCI module with LIN hardware and DMA support

Table ii. Terminology (Continued)

Terms

Description

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