MAC7200 datasheet(71/976 Pages) FREESCALE

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Terminology

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

lxxi

Program State

Flash array bit state that reads as a “0.”

Public Messages

Messages on the auxiliary pins for accomplishing common visibility and controllability

requirements

QDEC

Quadrature Decode

Resistor-Capacitor

Receive or RX FIFO

First-In-First-Out buffer for received data

Recessive Bit

A recessive bit loses the arbitration on the CAN bus. It is transmitted as ‘1.’

Reset Sequence

Coming out of reset, the CFM will read the Flash configuration field and load specific registers.

RQB

Interrupt Request Bus

RSD

Redundant Signed Digit: architecture how the ATD does the conversion

RSM

Result saving state machine

RTI

Real Time Interrupt - A timer with an independent clock which can run in system Doze or

Pseudo-Stop mode, and can be used for system wakeup.

RWCB

Read/Write Control Bus

RWW

Read While Write.

SAIC

Single Action Input Capture

SAOC

Single Action Output Compare

SAR

Successive Approximation Register: A method to adjust a reference voltage to an input voltage

SCI

Serial Communications Interface

SCK

Serial Communications Clock

Sclock

Serial clock (FlexCAN). This is the clock obtained by dividing the clock feeding the CAN engine

(either oscillator or bus clock) by a prescaler factor. The Sclock period defines the time

quantum for CAN protocol timing.

SCM

Self Clock Mode

Serialize

To convert data from a parallel format to a serial format.

Slave

A bus slave is a device that responds to a bus transaction, but never initiates a cycle on the bus.

SMB

Serial Message Buffer, an internal buffer not accessible by the end user.

SoC

System-on-a-chip.

Soft Reset

Global reset typically used by peripherals to re-initialize some of its registers, but not all of

them.

SPI

Serial Peripheral Interface

Slave Select. Signal from the SPI master to the SPI slave indicating which SPI slave device the

Master want to communicate with.

Stop Mode

This is a system low power mode in which all MCU clocks are stopped for maximum power

savings. Typically, when Stop Mode is requested, each module will put itself in a known state

and then send a Stop Acknowledge signal to inform the CPU that it can stop the clocks.

Table ii. Terminology (Continued)

Terms

Description

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