MAC7200 datasheet(57/976 Pages) FREESCALE

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MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

lvii

13-41

MCM Bus Aborts.................................................................................................................284

14-1

INTC Signals .......................................................................................................................288

14-2

INTC Bus Aborts .................................................................................................................288

14-3

INTC MAC71x1 versus MAC72xx Interrupt Source Assignment......................................289

14-4

ARM Interrupt Exception Summary....................................................................................292

14-5

INTC 32-bit Memory Map...................................................................................................293

14-6

Multiple Interrupt Controller IPS Memory Map .................................................................294

14-7

Interrupt Pending (IPRH, IPRL) Field Descriptions............................................................296

14-8

Interrupt Mask (IMRH, IMRL) Field Descriptions .............................................................297

14-9

Force Interrupt (INTFRCH, INTFRCL) Field Descriptions................................................298

14-10

Interrupt Configuration (ICONFIG) Field Descriptions......................................................299

14-11

Set Interrupt Mask (SIMR) Field Descriptions....................................................................301

14-12

Clear Interrupt Mask (CIMR) Field Descriptions................................................................302

14-13

Current Level Mask (CLMASK) Field Descriptions...........................................................303

14-14

Saved Level Mask (SLMASK) Field Descriptions .............................................................304

14-15

Interrupt Control Register n (ICRn) Field Descriptions ......................................................304

14-16

IRQ Interrupt Acknowledge Register (IRQIACK) Field Descriptions ...............................305

14-17

FIQ Interrupt Acknowledge Register (FIQIACK) Field Descriptions ................................306

14-18

Global IACK Steering Algorithm (3 Controllers) ...............................................................309

15-1

Crossbar Slave Port Addresses ............................................................................................314

15-2

MAC72xx AXBS Master and Slave Ports...........................................................................315

15-3

Module Memory Map ..........................................................................................................316

15-4

Priority Register Summary ..................................................................................................316

15-5

Priority Register Descriptions..............................................................................................317

15-6

Control Register Summary ..................................................................................................318

15-7

Control Register Descriptions..............................................................................................318

15-8

AXBS Bus Aborts................................................................................................................321

16-1

AIPS 32-bit byte lanes .........................................................................................................326

16-2

AIPS Register Memory Map ...............................................................................................330

16-3

MAC7200 Peripheral to Access Control Register Map.......................................................330

16-4

MPROT Field Descriptions .................................................................................................332

16-5

PACR Field Descriptions.....................................................................................................332

16-6

AIPS Bus Aborts..................................................................................................................335

16-7

MAC71x1 versus MAC72xx AIPS PACR Assignment ......................................................336

17-1

External Bus Auto Acknowledge Configuration .................................................................340

17-2

External Bus Port Size Configuration..................................................................................340

17-3

FlexBus Signal Summary ....................................................................................................341

17-4

Chip-Select Registers...........................................................................................................344

17-5

CSARn Field Descriptions...................................................................................................345

17-6

CSMRn Field Descriptions ..................................................................................................346

17-7

CSCRn Field Descriptions ...................................................................................................347

17-8

Bus Cycle States .................................................................................................................351

17-9

FlexBus Bus Aborts .............................................................................................................352

17-10

MAC71x1 to MAC72xx External Bus mapping .................................................................352

17-11

Global Chip Select Mode Configuration .............................................................................353

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