MC68HC708AS48 datasheet(23/396 Pages) FREESCALE

23 / 396 page

List of Figures

MC68HC708AS48 — Rev. 4.0

Advance Information

MOTOROLA

List of Figures

Figure

Title

Page

19-1

ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .319

19-2

ADC Status and Control Register (ADSCR). . . . . . . . . . . .324

19-3

ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . .327

19-4

ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . .327

20-1

BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332

20-2

BDLC Input/Output (I/O) Register Summary . . . . . . . . . . .333

20-3

BDLC Operating Modes State Diagram . . . . . . . . . . . . . . .334

20-4

BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337

20-5

BDLC Rx Digital Filter Block Diagram . . . . . . . . . . . . . . . .338

20-6

J1850 Bus Message Format (VPW) . . . . . . . . . . . . . . . . . .340

20-7

J1850 VPW Symbols with Nominal Symbol Times . . . . . .344

20-8

J1850 VPW Received Passive Symbol Times . . . . . . . . . .347

20-9

J1850 VPW Received Passive

EOF and IFS Symbol Times . . . . . . . . . . . . . . . . . . . . .348

20-10

J1850 VPW Received Active Symbol Times . . . . . . . . . . .349

20-11

J1850 VPW Received BREAK Symbol Times . . . . . . . . . .350

20-12

J1850 VPW Bitwise Arbitrations . . . . . . . . . . . . . . . . . . . . .351

20-13

BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352

20-14

BDLC Protocol Handler Outline . . . . . . . . . . . . . . . . . . . . .353

20-15

BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358

20-16

BDLC Analog and Roundtrip Delay Register (BARD) . . . .358

20-17

BDLC Control Register 1 (BCR1) . . . . . . . . . . . . . . . . . . . .360

20-18

BDLC Control Register 2 (BCR2) . . . . . . . . . . . . . . . . . . . .363

20-19

Types of In-Frame Response (IFR) . . . . . . . . . . . . . . . . . .367

20-20

BDLC State Vector Register (BSVR) . . . . . . . . . . . . . . . . .371

20-21

BDLC Data Register (BDR) . . . . . . . . . . . . . . . . . . . . . . . .373

21-1

SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384

21-2

SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385

21-3

BDLC Variable Pulse Width Modulation (VPW)

Symbol Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389

MC68HC708AS48 データシート(PDF) 23 Page - Freescale Semiconductor, Inc

MC68HC708AS48 データシート(HTML) 23 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード