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MC68HC708AS48 データシート(PDF) 26 Page - Freescale Semiconductor, Inc |
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MC68HC708AS48 データシート(HTML) 26 Page - Freescale Semiconductor, Inc |
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26 / 396 page  List of Tables List of Tables MC68HC708AS48 — Rev. 4.0 26 List of Tables MOTOROLA Table Title Page 15-1 Port A Pin Functions.............................................................190 15-2 Port B Pin Functions.............................................................193 15-3 Port C Pin Functions.............................................................196 15-4 Port D Pin Functions.............................................................200 15-5 Port E Pin Functions.............................................................204 15-6 Port F Pin Functions .............................................................207 15-7 Port G Pin Functions ............................................................210 16-1 Prescaler Selection...............................................................230 16-2 Mode, Edge, and Level Selection.........................................237 17-1 Start Bit Verification ..............................................................259 17-2 Data Bit Recovery.................................................................259 17-3 Stop Bit Recovery.................................................................260 17-4 Character Format Selection..................................................268 17-5 SCI Baud Rate Prescaling....................................................280 17-6 SCI Baud Rate Selection......................................................281 17-7 SCI Baud Rate Selection Examples .....................................282 18-1 Pin Name Conventions.........................................................285 18-2 I/O Register Addresses ........................................................285 18-3 SPI Interrupts........................................................................300 18-4 SPI Configuration .................................................................309 18-5 SPI Master Baud Rate Selection ..........................................315 19-1 Mux Channel Select .............................................................326 19-2 ADC Clock Divide Ratio........................................................328 20-1 BDLC J1850 Bus Error Summary.........................................357 20-2 BDLC Transceiver Delay .....................................................360 20-3 BDLC Rate Selection............................................................362 20-4 BDLC Transmit In-Frame Response Control Bit Priority Encoding............................................366 20-5 BDLC Interrupt Sources .......................................................371 23-1 MC Order Numbers ..............................................................393 |
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