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UPD17708 データシート(PDF) 246 Page - NEC |
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UPD17708 データシート(HTML) 246 Page - NEC |
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246 / 356 page ![]() 246 µPD17704, 17705, 17707, 17708, 17709 Figure 16-17. Configuration of Serial I/O1 Mode Selection Register 16.3.3 Clock counter The clock counter is a wrap-around counter that counts the rising edges of the clock. Because this counter directly reads the status of the clock pin, whether the clock is an internal clock or external clock cannot be identified. The contents of the clock counter cannot be directly read by software. Name Flag symbol b3 S I O 1 T S b2 S I O 1 H I Z b1 S I O 1 C K 1 b0 S I O 1 C K 0 Address 1DH Read/Write R/W Serial I/O1 mode selection Power-ON reset WDT&SP reset CE reset Clock stop 0 1 0 1 0 0 0 0 External clock input 187.50 kHz 375.00 kHz 46.875 kHz Selects shift clock of serial interface 1 0 0 0 0 0 0 0 0 0 0 1 1 General-purpose I/O port Serail data output pin Selects function of P0B1/SO1 pin 0 1 0 0 0 0 Stops (wait status) Starts Start or stops operation of serial communication 0 1 |
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