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UPD17708 データシート(PDF) 17 Page - NEC |
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UPD17708 データシート(HTML) 17 Page - NEC |
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17 / 356 page  17 µPD17704, 17705, 17707, 17708, 17709 (2) P0A (P0A3/SDA, P0A2/SCL) (I/O) Note This is an internal signal that is output when the clock stop instruction is executed, and its circuit is designed not to increase the current consumption due to noise even if it is floated. (3) P1B (P1B3, P1B2/PWM2, P1B1/PWM1, P1B0/PWM0) (output) (4) P0D (P0D3/AD3, P0D2/AD2, P0D1/AD1, P0D0/AD0) (input) Note This is an internal signal that is output when the clock stop instruction is executed, and its circuit is designed not to increase the current consumption due to noise even if it is floated. VDD CKSTOPNote VDD CKSTOPNote A/D converter P0DPLD flag High-ON resistance |
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