JS28F256P30T85 datasheet(65/102 Pages) INTEL

65 / 102 page

1-Gbit P30 Family

Datasheet

Intel StrataFlash® Embedded Memory (P30)

April 2005

Order Number: 306666, Revision: 001

Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data

programming to the array. For BEFP, the count value for buffer loading is always the maximum

buffer size of 32 words. During the buffer-loading sequence, data is stored to sequential buffer

locations starting at address 0x00. Programming of the buffer contents to the flash memory array

starts as soon as the buffer is full. If the number of words is less than 32, the remaining buffer

locations must be filled with 0xFFFF.

Caution:

The buffer must be completely filled for programming to occur. Supplying an address outside of the

current block's range during a buffer-fill sequence causes the algorithm to exit immediately. Any

data previously loaded into the buffer during the fill cycle is not programmed into the array.

The starting address for data entry must be buffer size aligned, if not the BEFP algorithm will be

aborted and the program fails and (SR[4]) flag will be set.

Data words from the write buffer are directed to sequential memory locations in the flash memory

array; programming continues from where the previous buffer sequence ended. The host

programming system must poll SR[0] to determine when the buffer program sequence completes.

SR[0] cleared indicates that all buffer data has been transferred to the flash array; SR[0] set

indicates that the buffer is not available yet for the next fill cycle. The host system may check full

status for errors at any time, but it is only necessary on a block basis after BEFP exit. After the

buffer fill cycle, no write cycles should be issued to the device until SR[0] = 0 and the device is

ready for the next buffer fill.

Note:

Any spurious writes are ignored after a buffer fill operation and when internal program is

proceeding.

The host programming system continues the BEFP algorithm by providing the next group of data

words to be written to the buffer. Alternatively, it can terminate this phase by changing the block

address to one outside of the current block’s range.

The Program/Verify phase concludes when the programmer writes to a different block address;

data supplied must be 0xFFFF. Upon Program/Verify phase completion, the device enters the

BEFP Exit phase.

11.3.4

BEFP Exit Phase

When SR[7] is set, the device has returned to normal operating conditions. A full status check

should be performed at this time to ensure the entire block programmed successfully. When exiting

the BEFP algorithm with a block address change, the read mode will not change. After BEFP exit,

any valid command can be issued to the device.

11.4

Program Suspend

Issuing the Program Suspend command while programming suspends the programming operation.

This allows data to be accessed from the device other than the one being programmed. The

Program Suspend command can be issued to any device address. A program operation can be

suspended to perform reads only. Additionally, a program operation that is running during an erase

suspend can be suspended to perform a read operation (see Figure 41, “Program Suspend/Resume

Flowchart” on page 86).

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