JS28F256P30T85 datasheet(22/102 Pages) INTEL

22 / 102 page

1-Gbit P30 Family

April 2005

Intel StrataFlash® Embedded Memory (P30)

Datasheet

Order Number: 306666, Revision: 001

4.3

SCSP Configurations

WP#

Input

WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock-

down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function

enabling blocks to be erased or programmed using software commands.

VPP

Power/

lnput

Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory

contents cannot be altered when VPP ≤ VPPLK. Block erase and program at invalid VPP voltages

should not be attempted.

Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops

from the system supply, the VIH level of VPP can be as low as VPPL min. VPP must remain above VPPL

min to perform in-system flash modification. VPP may be 0 V during read operations.

VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500

cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of

this pin at 9 V may reduce block cycling capability.

VCC

Power

Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when

VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted.

VCCQ

Power

Output Power Supply: Output-driver source voltage.

VSS

Power

Ground: Connect to system ground. Do not float any VSS connection.

RFU

—

Reserved for Future Use: Reserved by Intel for future device functionality and enhancement. These

should be treated in the same way as a Do Not Use (DU) signal.

—

Do Not Use: Do not connect to any other signal, or power supply; must be left floating.

—

No Connect: No internal connection; can be driven or floated.

Table 4.

QUAD+ SCSP Signal Descriptions (Sheet 2 of 2)

Symbol

Type

Name and Function

Table 5.

Stacked Easy BGA Chip Select Logic

Stack Combination

Selected Flash

Die #1

Selected Flash

Die #2

1-die

F1-CE#

2-die

F1-CE# + A25 (VIL)

F1-CE# + A25 (VIH)

Table 6.

QUAD+ SCSP Chip Select Logic

Stack

Combination

Selected Flash

Die #1

Selected Flash

Die #2

Selected Flash

Die #3

Selected Flash

Die #4

1-die

F1-CE#

2-die

F1-CE# + A24 (VIL)

F1-CE# + A24 (VIH)-

4-die

F1-CE# + A24 (VIL)

F1-CE# + A24 (VIH)

F2-CE# + A24 (VIL)

F2-CE# + A24 (VIH)

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