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JS28F256P30T85 データシート(PDF) 60 Page - Intel Corporation |
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JS28F256P30T85 データシート(HTML) 60 Page - Intel Corporation |
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60 / 102 page  1-Gbit P30 Family April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet 60 Order Number: 306666, Revision: 001 boundary, the worst case output delay is one clock cycle less than the first access Latency Count. This delay can take place only once, and doesn’t occur if the burst sequence does not cross a device-row boundary. WAIT informs the system of this delay when it occurs. 10.3.9 Burst Length The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word. Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see Table 25, “Burst Sequence Word Ordering” on page 59). When a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the “burstable” address space. |
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