JS28F256P30T85 datasheet(20/102 Pages) INTEL

20 / 102 page

1-Gbit P30 Family

April 2005

Intel StrataFlash® Embedded Memory (P30)

Datasheet

Order Number: 306666, Revision: 001

4.2

Signal Descriptions

This section has signal descriptions for the various P30 packages.

Table 3.

TSOP and Easy BGA Signal Descriptions (Sheet 1 of 2)

Symbol

Type

Name and Function

A[MAX:1]

Input

ADDRESS INPUTS: Device address inputs. 64-Mbit: A[22:1]; 128-Mbit: A[23:1]; 256-Mbit: A[24:1];

512-Mbit: A[25:1].

See Table 5 on page 22 and Figure 10 on page 23 for 512-Mbit addressing.

DQ[15:0]

Input/

Output

DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during

memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls

float when the CE# or OE# are deasserted. Data is internally latched during writes.

ADV#

Input

ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on

the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.

In asynchronous mode, the address is latched when ADV# going high or continuously flows through

if ADV# is held low.

WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.

CE#

Input

FLASH CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When

asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When

deasserted, the associated flash die is deselected, power is reduced to standby levels, data and

WAIT outputs are placed in high-Z state.

WARNING: All chip enables must be high when device is not in use.

CLK

Input

CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode.

During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the

next valid CLK edge with ADV# low, whichever occurs first.

WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.

OE#

Input

OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read

cycles. OE# high places the data outputs and WAIT in High-Z.

RST#

Input

RESET: Active low input. RST# resets internal automation and inhibits write operations. This

provides data protection during power transitions. RST# high enables normal operation. Exit from

reset places the device in asynchronous read array mode.

WAIT

Output

WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration

VOH when CE# and OE# are VIL. WAIT is high-Z if CE# or OE# is VIH.

•

In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and

valid data when deasserted.

•

In asynchronous page mode, and all write modes, WAIT is deasserted.

WE#

Input

WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched

on the rising edge of WE#.

WP#

Input

WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock-

down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function

enabling blocks to be erased or programmed using software commands.

VPP

Power/

Input

Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory

contents cannot be altered when VPP ≤ VPPLK. Block erase and program at invalid VPP voltages

should not be attempted.

Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops

from the system supply, the VIH level of VPP can be as low as VPPL min. VPP must remain above VPPL

min to perform in-system flash modification. VPP may be 0 V during read operations.

VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500

cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of

this pin at 9 V may reduce block cycling capability.

VCC

Power

Device Core Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when

VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted.

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