JS28F256P30T85 datasheet(54/102 Pages) INTEL

54 / 102 page

1-Gbit P30 Family

April 2005

Intel StrataFlash® Embedded Memory (P30)

Datasheet

Order Number: 306666, Revision: 001

However, for a synchronous non-array read, the same word of data will be output on successive

clock edges until the burst length requirements are satisfied. Refer to the following waveforms for

more detailed information:

• Figure 19, “Synchronous Single-Word Array or Non-array Read Timing” on page 39

• Figure 20, “Continuous Burst Read, showing an Output Delay Timing” on page 40

• Figure 21, “Synchronous Burst-Mode Four-Word Read Timing” on page 41

10.3

Read Configuration Register

The Read Configuration Register (RCR) is used to select the read mode (synchronous or

asynchronous), and it defines the synchronous burst characteristics of the device. To modify RCR

settings, use the Configure Read Configuration Register command (see Section 9.2, “Device

Commands” on page 50).

RCR contents can be examined using the Read Device Identifier command, and then reading from

offset 0x05 (see Section 14.2, “Read Device Identifier” on page 76).

The RCR is shown in Table 22. The following sections describe each RCR bit.

Table 22.

Read Configuration Register Description (Sheet 1 of 2)

Read Configuration Register (RCR)

Read

Mode

RES

Latency Count

WAIT

Polarity

Data

Hold

WAIT

Delay

Burst

Seq

CLK

Edge

RES

Burst

Wrap

Burst Length

LC[2:0]

BL[2:0]

Bit

Name

Description

Read Mode (RM)

0 = Synchronous burst-mode read

1 = Asynchronous page-mode read (default)

Reserved (R)

Reserved bits should be cleared (0)

13:11

Latency Count (LC[2:0])

010 =Code 2

011 =Code 3

100 =Code 4

101 =Code 5

110 =Code 6

111 =Code 7 (default)

(Other bit settings are reserved)

Wait Polarity (WP)

0 =WAIT signal is active low

1 =WAIT signal is active high (default)

Data Hold (DH)

0 =Data held for a 1-clock data cycle

1 =Data held for a 2-clock data cycle (default)

Wait Delay (WD)

0 =WAIT deasserted with valid data

1 =WAIT deasserted one data cycle before valid data (default)

Burst Sequence (BS)

0 =Reserved

1 =Linear (default)

Clock Edge (CE)

0 = Falling edge

1 = Rising edge (default)

5:4

Reserved (R)

Reserved bits should be cleared (0)

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