JS28F256P30T85 datasheet(41/102 Pages) INTEL

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1-Gbit P30 Family

Datasheet

Intel StrataFlash® Embedded Memory (P30)

April 2005

Order Number: 306666, Revision: 001

Note:

WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during

initial latency and deasserted during valid data (RCR[10] = 0, Wait asserted low).

7.4

AC Write Specifications

Figure 21.

Synchronous Burst-Mode Four-Word Read Timing

R307

R10

R304

R305

R304

R17

R15

R303

R106

R102

R105

R101

R306

R302

R301

CLK [C]

Address [A]

ADV# [V]

CE# [E]

OE# [G]

WAIT [T]

Data [D/Q]

Table 18.

AC Write Specifications (Sheet 1 of 2)

Num

Symbol

Parameter

Min

Max

Units

Notes

PHWL

RST# high recovery to WE# low

150

1,2,3

ELWL

CE# setup to WE# low

1,2,3

WLWH

WE# write pulse width low

1,2,4

DVWH

Data setup to WE# high

1,2

AVWH

Address setup to WE# high

WHEH

CE# hold from WE# high

WHDX

Data hold from WE# high

WHAX

Address hold from WE# high

WHWL

WE# pulse width high

1,2,5

W10

VPWH

VPP setup to WE# high

200

1,2,3,7

W11

QVVL

VPP hold from Status read

W12

QVBL

WP# hold from Status read

1,2,3,7

W13

BHWH

WP# setup to WE# high

200

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