JS28F256P30T85 datasheet(72/102 Pages) INTEL

72 / 102 page

1-Gbit P30 Family

April 2005

Intel StrataFlash® Embedded Memory (P30)

Datasheet

Order Number: 306666, Revision: 001

13.3

Protection Registers

The device contains 17 Protection Registers (PRs) that can be used to implement system security

measures and/or device identification. Each Protection Register can be individually locked.

The first 128-bit Protection Register is comprised of two 64-bit (8-word) segments. The lower 64-

bit segment is pre-programmed at the Intel factory with a unique 64-bit number. The other 64-bit

segment, as well as the other sixteen 128-bit Protection Registers, are blank. Users can program

these registers as needed. When programmed, users can then lock the Protection Register(s) to

prevent additional bit programming (see Figure 33, “Protection Register Map” on page 73).

The user-programmable Protection Registers contain one-time programmable (OTP) bits; when

programmed, register bits cannot be erased. Each Protection Register can be accessed multiple

times to program individual bits, as long as the register remains unlocked.

Each Protection Register has an associated Lock Register bit. When a Lock Register bit is

programmed, the associated Protection Register can only be read; it can no longer be programmed.

Additionally, because the Lock Register bits themselves are OTP, when programmed, Lock

unlocked.

JS28F256P30T85 データシート(PDF) 72 Page - Intel Corporation