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JS28F256P30T85 データシート(PDF) 36 Page - Intel Corporation |
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JS28F256P30T85 データシート(HTML) 36 Page - Intel Corporation |
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36 / 102 page  1-Gbit P30 Family April 2005 Intel StrataFlash® Embedded Memory (P30) Datasheet 36 Order Number: 306666, Revision: 001 R305 tCHQX Output hold from CLK 3 - ns 1,5 R306 tCHAX Address hold from CLK 10 - ns 1,4,5 R307 tCHTV CLK to WAIT valid - 20 ns 1,5 R311 tCHVL CLK Valid to ADV# Setup 3 - ns 1 R312 tCHTX WAIT Hold from CLK 3 - ns 1,5 NOTES: 1. See Figure 13, “AC Input/Output Reference Waveform” on page 33 for timing measurements and max allowable input slew rate. 2. OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV. 3. Sampled, not 100% tested. 4. Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first. 5. Applies only to subsequent synchronous reads. 6. See your local Intel representative for designs requiring higher than 40 MHz synchronous operation. Table 16. AC Read Specifications for 64/128-Mbit Densities (Sheet 2 of 2) Num Symbol Parameter Min Max Unit Notes Table 17. AC Read Specifications for 256/512-Mbit and 1-Gbit Densities (Sheet 1 of 2) Num Symbol Parameter Speed Min Max Unit Notes Asynchronous Specifications R1 tAVAV Read cycle time Vcc = 1.8 V – 2.0 V 85 - ns Vcc = 1.7 V – 2.0 V 88 - R2 t AVQV Address to output valid Vcc = 1.8 V – 2.0 V -85 ns Vcc = 1.7 V – 2.0 V -88 R3 t ELQV CE# low to output valid Vcc = 1.8 V – 2.0 V -85 ns Vcc = 1.7 V – 2.0 V -88 R4 t GLQV OE# low to output valid - 25 ns 1,2 R5 tPHQV RST# high to output valid - 150 ns 1 R6 tELQX CE# low to output in low-Z 0 - ns 1,3 R7 tGLQX OE# low to output in low-Z 0 - ns 1,2,3 R8 tEHQZ CE# high to output in high-Z - 24 ns 1,3 R9 tGHQZ OE# high to output in high-Z - 24 ns R10 tOH Output hold from first occurring address, CE#, or OE# change 0 - ns R11 tEHEL CE# pulse width high 20 - ns 1 R12 tELTV CE# low to WAIT valid - 17 ns R13 tEHTZ CE# high to WAIT high-Z - 20 ns 1,3 R15 tGLTV OE# low to WAIT valid - 17 ns 1 R16 tGLTX OE# low to WAIT in low-Z 0 - ns 1,3 R17 tGHTZ OE# high to WAIT in high-Z - 20 ns Latching Specifications |
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