データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

JS28F256P30T85 データシート(PDF) 59 Page - Intel Corporation

部品番号 JS28F256P30T85
部品情報  Intel StrataFlash Embedded Memory
PDF  102 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  INTEL [Intel Corporation]
ホームページ  http://www.intel.com
Logo INTEL - Intel Corporation

JS28F256P30T85 データシート(HTML) 59 Page - Intel Corporation

Back Button JS28F256P30T85 Datasheet HTML 55Page - Intel Corporation JS28F256P30T85 Datasheet HTML 56Page - Intel Corporation JS28F256P30T85 Datasheet HTML 57Page - Intel Corporation JS28F256P30T85 Datasheet HTML 58Page - Intel Corporation JS28F256P30T85 Datasheet HTML 59Page - Intel Corporation JS28F256P30T85 Datasheet HTML 60Page - Intel Corporation JS28F256P30T85 Datasheet HTML 61Page - Intel Corporation JS28F256P30T85 Datasheet HTML 62Page - Intel Corporation JS28F256P30T85 Datasheet HTML 63Page - Intel Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 59 / 102 page
background image
1-Gbit P30 Family
Datasheet
Intel StrataFlash® Embedded Memory (P30)
April 2005
Order Number: 306666, Revision: 001
59
10.3.5
WAIT Delay
The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during synchronous burst
reads. WAIT can be asserted either during or one data cycle before valid data is output on
DQ[15:0]. When WD is set, WAIT is deasserted one data cycle before valid data (default). When
WD is cleared, WAIT is deasserted during valid data.
10.3.6
Burst Sequence
The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst sequence is
supported. Table 25 shows the synchronous burst sequence for all burst lengths, as well as the
effect of the Burst Wrap (BW) setting.
10.3.7
Clock Edge
The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK. This clock
edge is used at the start of a burst cycle, to output synchronous data, and to assert/deassert WAIT.
10.3.8
Burst Wrap
The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length accesses
wrap within the selected word-length boundaries or cross word-length boundaries. When BW is
set, burst wrapping does not occur (default). When BW is cleared, burst wrapping occurs.
When performing synchronous burst reads with BW set (no wrap), an output delay may occur
when the burst sequence crosses its first device-row (16-word) boundary. If the burst sequence’s
start address is 4-word aligned, then no delay occurs. If the start address is at the end of a 4-word
Table 25.
Burst Sequence Word Ordering
Start
Addr.
(DEC)
Burst Wrap
(RCR[3])
Burst Addressing Sequence (DEC)
4-Word Burst
(BL[2:0] = 0b001)
8-Word Burst
(BL[2:0] = 0b010)
16-Word Burst
(BL[2:0] = 0b011)
Continuous Burst
(BL[2:0] = 0b111)
0
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4…14-15
0-1-2-3-4-5-6-…
1
0
1-2-3-0
1-2-3-4-5-6-7-0
1-2-3-4-5…15-0
1-2-3-4-5-6-7-…
2
0
2-3-0-1
2-3-4-5-6-7-0-1
2-3-4-5-6…15-0-1
2-3-4-5-6-7-8-…
3
0
3-0-1-2
3-4-5-6-7-0-1-2
3-4-5-6-7…15-0-1-2
3-4-5-6-7-8-9-…
40
4-5-6-7-0-1-2-3
4-5-6-7-8…15-0-1-2-3
4-5-6-7-8-9-10…
50
5-6-7-0-1-2-3-4
5-6-7-8-9…15-0-1-2-3-4
5-6-7-8-9-10-11…
60
6-7-0-1-2-3-4-5
6-7-8-9-10…15-0-1-2-3-4-5 6-7-8-9-10-11-12-…
70
7-0-1-2-3-4-5-6
7-8-9-10…15-0-1-2-3-4-5-6 7-8-9-10-11-12-13…
14
0
14-15-0-1-2…12-13
14-15-16-17-18-19-20-…
15
0
15-0-1-2-3…13-14
15-16-17-18-19-20-21-…
0
1
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4…14-15
0-1-2-3-4-5-6-…
1
1
1-2-3-4
1-2-3-4-5-6-7-8
1-2-3-4-5…15-16
1-2-3-4-5-6-7-…
2
1
2-3-4-5
2-3-4-5-6-7-8-9
2-3-4-5-6…16-17
2-3-4-5-6-7-8-…
3
1
3-4-5-6
3-4-5-6-7-8-9-10
3-4-5-6-7…17-18
3-4-5-6-7-8-9-…
41
4-5-6-7-8-9-10-11
4-5-6-7-8…18-19
4-5-6-7-8-9-10…
51
5-6-7-8-9-10-11-12
5-6-7-8-9…19-20
5-6-7-8-9-10-11…
61
6-7-8-9-10-11-12-13
6-7-8-9-10…20-21
6-7-8-9-10-11-12-…
71
7-8-9-10-11-12-13-14
7-8-9-10-11…21-22
7-8-9-10-11-12-13…
14
1
14-15-16-17-18…28-29
14-15-16-17-18-19-20-…
15
1
15-16-17-18-19…29-30
15-16-17-18-19-20-21-…



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com