JS28F256P30T85 datasheet(74/102 Pages) INTEL

74 / 102 page

1-Gbit P30 Family

April 2005

Intel StrataFlash® Embedded Memory (P30)

Datasheet

Order Number: 306666, Revision: 001

The device programs the 64-bit and 128-bit user-programmable Protection Register data 16 bits at

a time (see Figure 47, “Protection Register Programming Flowchart” on page 92). Issuing the

Program Protection Register command outside of the Protection Register’s address space causes a

program error (SR[4] set). Attempting to program a locked Protection Register causes a program

error (SR[4] set) and a lock error (SR[1] set).

13.3.3

Locking the Protection Registers

Each Protection Register can be locked by programming its respective lock bit in the Lock

issuing the Program Lock Register command, followed by the desired Lock Register data (see

Section 9.2, “Device Commands” on page 50). The physical addresses of the Lock Registers are

0x80 for register 0 and 0x89 for register 1. These addresses are used when programming the lock

registers (see Table 29, “Device Identifier Information” on page 77).

Bit 0 of Lock Register 0 is already programmed at the factory, locking the lower, pre-programmed

64-bit region of the first 128-bit Protection Register containing the unique identification number of

the device. Bit 1 of Lock Register 0 can be programmed by the user to lock the user-programmable,

64-bit region of the first 128-bit Protection Register. When programming Bit 1 of Lock Register 0,

all other bits need to be left as ‘1’ such that the data programmed is 0xFFFD.

Lock Register 1 controls the locking of the upper sixteen 128-bit Protection Registers. Each of the

16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit Protection Registers.

Programming a bit in Lock Register 1 locks the corresponding 128-bit Protection Register.

Caution:

After being locked, the Protection Registers cannot be unlocked.

JS28F256P30T85 データシート(PDF) 74 Page - Intel Corporation