JS28F256P30T85 datasheet(98/102 Pages) INTEL

98 / 102 page

1-Gbit P30 Family

April 2005

Intel StrataFlash® Embedded Memory (P30)

Datasheet

Order Number: 306666, Revision: 001

Table 38.

Protection Register Information

Table 39.

Burst Read Information

Offset

(1)

Length

Description

Hex

P = 10Ah

(Optional flash features and commands)

Add.

Code

Value

(P+E)h

118:

--02

(P+F)h

Protection Field 1: Protection Description

119:

--80

80h

(P+10)h

This field describes user-available One Time Programmable

11A:

--00

00h

(P+11)h

(OTP) Protection register bytes. Some are pre-programmed

11B:

--03

8 byte

(P+12)h

11C:

--03

8 byte

(P+13)h

Protection Field 2: Protection Description

11D:

--89

89h

(P+14)h

11E:

--00

00h

(P+15)h

11F:

--00

00h

(P+16)h

120:

--00

00h

(P+17)h

121:

--00

(P+18)h

bits 40–47 = “n”

∴ n = factory pgm'd groups (high byte)

122:

--00

(P+19)h

123:

--00

(P+1A)h

124:

--10

(P+1B)h

125:

--00

(P+1C)h

126:

--04

bits 48–55 = “n” \ 2n = factory programmable bytes/group

bits 56–63 = “n”

∴ n = user pgm'd groups (low byte)

bits 64–71 = “n”

∴ n = user pgm'd groups (high byte)

bits 72–79 = “n”

∴ 2n = user programmable bytes/group

with device-unique serial numbers. Others are user

programmable. Bits 0–15 point to the Protection register Lock

byte, the section’s first byte. The following bytes are factory

pre-programmed and user-programmable.

bits 0–7 = Lock/bytes Jedec-plane physical low address

bits 8–15 = Lock/bytes Jedec-plane physical high address

bits 16–23 = “n” such that 2

n = factory pre-programmed bytes

bits 24–31 = “n” such that 2

n = user programmable bytes

Bits 0–31 point to the Protection register physical Lock-word

address in the Jedec-plane.

Following bytes are factory or user-programmable.

bits 32–39 = “n”

∴ n = factory pgm'd groups (low byte)

Number of Protection register fields in JEDEC ID space.

“00h,” indicates that 256 protection fields are available

Offset

(1)

Length

Description

Hex

P = 10Ah

(Optional flash features and commands)

Add.

Code

Value

(P+1D)h

127:

--03

8 byte

(P+1E)h

128:

--04

(P+1F)h

129:

--01

(P+20)h

Synchronous mode read capability configuration 2

12A:

--02

(P+21)h

Synchronous mode read capability configuration 3

12B:

--03

(P+22)h

Synchronous mode read capability configuration 4

12C:

--07

Cont

Page Mode Read capability

bits 0–7 = “n” such that 2

n HEX value represents the number of

read-page bytes. See offset 28h for device word width to

determine page-mode data output width. 00h indicates no

read page buffer.

Number of synchronous mode read configuration fields that

follow. 00h indicates no burst capability.

Synchronous mode read capability configuration 1

Bits 3–7 = Reserved

bits 0–2 “n” such that 2

n+1 HEX value represents the

maximum number of continuous synchronous reads when

the device is configured for its maximum word width. A value

of 07h indicates that the device is capable of continuous

linear bursts that will output data until the internal burst

counter reaches the end of the device’s burstable address

space. This field’s 3-bit value can be written directly to the

Read Configuration Register bits 0–2 if the device is

configured for its maximum word width. See offset 28h for

word width to determine the burst data output width.

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