L9803 datasheet(55/126 Pages) STMICROELECTRONICS

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L9803

On-Chip Peripherals

55/126

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = OC1E Output Compare 1 Enable.

Output Compare 1 function is enabled, but the OCMP1 pin is a general I/O.

Output Compare 1 function is enabled, the OCMP1 pin is dedicated to the Output

Compare 1 capability of the timer.

Bit 6 = OC2E Output Compare 2 Enable.

Output Compare 2 function is enabled, but the OCMP2 pin is a general I/O.

Output Compare 2 function is enabled, the OCMP2 pin is dedicated to the Output

Compare 2 capability of the timer.

Bit 5 = OPM One Pulse Mode.

One Pulse Mode is not active.

One Pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the

OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated

pulse depends on the contents of the OCR1 register.

Bit 4 = PWM Pulse Width Modulation.

PWM mode is not active.

PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length

of the pulse depends on the value of OCR1 register; the period depends on the value of

OCR2 register.

Bit 3, 2 = CC1-CC0 Clock Control.

The value of the timer clock depends on these bits:

OC1E

OC2E

OPM

PWM

CC1

CC0

IEDG2

EXEDG

Table 9.

Clock Control Bits

CC1

CC0

Timer Clock

fCPU / 4

fCPU / 2

fCPU / 8

External Clock where available

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