| データシートサーチシステム |
|
L9803 データシート(PDF) 99 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
L9803 データシート(HTML) 99 Page - STMicroelectronics |
|
99 / 126 page ![]() L9803 On-Chip Peripherals 99/126 Figure 46. Example - Power Bridge Waveform, PWM Up Brake Driving Mode 5.8.6 Register Description The power section is controlled by the microcontroller through the following register: POWER BRIDGE CONTROL STATUS REGISTER (PBCSR) Address: 0021h - Read/Write Reset Value: 00000000 Bit 0 = EN: Power Bridge enable. When reset the bridge is disabled and OUTL and OUTR are in high impedance condition. Bit 1= PWM_EN: PWM driving enable. When reset the bridge is driven directly by IN1 and IN2 bit (Direct Mode). When set the driving is made by PWM1 and/or PWM2 bit according to the Operation Mode selected by IN1 and IN2 bit. Bit 2= IN1: Left Half Bridge control bit if PWM_EN=0, driving mode selection bit if PWM_EN=1. Bit 3= IN2: Right Half Bridge control bit if PWM_EN=0, driving mode selection bit if PWM_EN=1. PWM1 DIR UL DL UR DR OUTL OUTR 7 0 PIE OVT SC DIR IN2 IN1 PWM_EN EN |
|
リンク URL |
| ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | データシートへのリンク | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |