L9803 datasheet(63/126 Pages) STMICROELECTRONICS

部品番号	L9803

部品情報	Super smart power motor driver with 8-Bit MCU, RAM, EEPROM, ADC, WDG, Timers, PWM and H-bridge driver

PDF	126 Pages

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メーカー	STMICROELECTRONICS [STMicroelectronics]

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L9803

On-Chip Peripherals

63/126

Figure 29.

PWM Cycle

Note:

If the CYREG value is minor or equal than DUTYREG value, PWM output remains set. With

a DUTYREG value of 0000h, the PWM output is permanently at low level, no matter of the

value of CYREG. With a DUTYREG value of FFFFh, the PWM output is permanently at high

level.

Interrupt Request

The EN_INT bit in CONREG register must be set to enable the interrupt generation. When

the 16 bits of the counter roll-over CYCLEREG value, interrupt request is set.

The interrupt request is cleared when any of the PWM registers is written.

Figure 30.

PWM Generation

5.3.3

The PWM is associated with a 8-bit control registers, and with two 16-bit data registers,

each split in two 8-bit registers.

PWM CYCLE REGISTER LOW (CYREGL)

PWM1 Register Address: 0011h

PWM2 Register Address: 0019h

Read/Write

Reset Value: 0000 0000 (00h)

Counter

Counter is reset

OUT PWM = 1

Counter

= CYREG

OUT PWM = 0

When

= DUTYREG

Pulse Width Modulation cycle

COUNTER

CYREG

COMPARE

VALUE

000

PWM OUTPUT

(INTERNAL CLOCK) x Cyreg_value

value

Interrupt Generation

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