L9803 datasheet(80/126 Pages) STMICROELECTRONICS

80 / 126 page

On-Chip Peripherals

L9803

80/126

determine the stability of the network. Moreover, as one of the node status bits (EPSV

or BOFF of the CSR register) changes, an interrupt is generated if the SCIE bit is set in

the ICR Register. Refer to Figure 40.

Figure 40.

CAN Error State Diagram

Bit Timing Logic

The bit timing logic monitors the serial bus-line and performs sampling and adjustment of

the sample point by synchronizing on the start-bit edge and resynchronizing on following

edges.

Its operation may be explained simply when the nominal bit time is divided into three

segments as follows:

●

Synchronisation segment (SYNC_SEG): a bit change is expected to lie within this

time segment. It has a fixed length of one time quanta (1 x tCAN).

●

Bit segment 1 (BS1): defines the location of the sample point. It includes the

PROP_SEG and PHASE_SEG1 of the CAN standard. Its duration is programmable

between 1 and 16 time quanta but may be automatically lengthened to compensate for

positive phase drifts due to differences in the frequency of the various nodes of the

network.

●

Bit segment 2 (BS2): defines the location of the transmit point. It represents the

PHASE_SEG2 of the CAN standard. Its duration is programmable between 1 and 8

time quanta but may also be automatically shortened to compensate for negative

phase drifts.

●

Resynchronization Jump Width (RJW): defines an upper bound to the amount of

lengthening or shortening of the bit segments. It is programmable between 1 and 4 time

quanta.

To guarantee the correct behaviour of the CAN controller, SYNC_SEG + BS1 + BS2 must

be greater than or equal to 5 time quanta.

For a detailed description of the CAN resynchronization mechanism and other bit timing

configuration constraints, please refer to the CAN Specification - Bosh - Version 2.

ERROR PASSIVE

When TECR or RECR > 127, the EPSV bit gets set

When TECR and RECR < 128,

and the EPSV bit gets cleared

ERROR ACTIVE

BUS OFF

When TECR > 255 the BOFF bit gets set

When 128 * 11 recessive bits occur:

- the BOFF bit gets cleared

- the TECR register gets cleared

- the RECR register gets cleared

the EPSV bit gets cleared

L9803 データシート(PDF) 80 Page - STMicroelectronics

L9803 データシート(HTML) 80 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード